Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/27/2024 and 09/24/2024 are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In the present instance, claim 4 recites “another end portion in the third direction of the first wiring portion”. However, paragraph [0068] of the specification discloses “the other end portion E2b in the Y-direction of the first wiring portion 12a”, the Y-direction being defined as a second direction in paragraph [0024]. Therefore, it is unclear whether claim 4’s “another end portion in the third direction” refers to (a) an opposite third-direction end of the first wiring portion- not described in the specification, or (b) the second-direction side described in parargraph [0068] and shown in FIG. 5- in which case the claim’s use of “third direction” is inconsistent with, and unsupported by disclosure.
For examination purpose, the claim limitation will be examined as “second direction of the first wiring portion”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al. (US 6057558 A) in view of Tokuda (US 9196720 B2).
Regarding claim 1, Yamamoto et al. teaches semiconductor device (silicon carbide semiconductor device) comprising:
a first electrode (drain electrode layer 13);
a first semiconductor region (n- -type epitaxial layer 2) of a first conductivity type (n-type) provided on the first electrode;
a second semiconductor region (p-type epitaxial layer 3) of a second conductivity type (p-type);
a third semiconductor region (n+ -type source region 5) of the first conductivity type provided on the second semiconductor region;
a conductor (gate electrode layer 10) provided on the first semiconductor region via an insulating layer (gate oxide film 9), the conductor including
a first gate electrode portion (see first annotated FIG. 1) facing the second semiconductor region in a second direction (y-direction) perpendicular to the first direction, and extending in a third direction (x-direction) perpendicular to the first direction and the second direction,
a second gate electrode portion (see first annotated FIG. 1) extending in the third direction, the second semiconductor region being positioned between (FIG. 1) the first gate electrode portion and the second gate electrode portion,
a first wiring portion (see first annotated FIG. 1) extending in the third direction (x-direction),
a first connection portion (first annotated FIG. 1, gate electrode side S5) connected between a first end portion (see first annotated FIG. 1) in the third direction of the first gate electrode portion (see first annotated FIG. 1) and an end portion (see first annotated FIG. 1) in the third direction of the first wiring portion, and
a second connection portion (first annotated FIG. 1, gate electrode side S6) connected between a second end portion (see first annotated FIG. 1) in the third direction of the second gate electrode portion (see first annotated FIG. 1) and the end portion of the first wiring portion,
a position (first annotated FIG. 1, labeled “Pos 2”) in the second direction (y-direction) of the first wiring portion being between a position (first annotated FIG. 1, labeled “Pos 1”) in the second direction of the first gate electrode portion and a position (first annotated FIG. 1, labeled “Pos 3”) in the second direction of the second gate electrode portion, the first connection portion and the second connection portion having inclined surfaces ((36), side face 7a smooth curved surface and (20), side face 7a of the trench 7 parallel with [1100] direction, e.g. sides S2 and S3) that are inclined with respect to the second direction and the third direction; and
a second electrode (source electrode layer 12) provided on the second semiconductor region and the third semiconductor region.
Yamamoto et al. does not explicitly teach a semiconductor device comprising a first portion and second portion. However, Tokuda teaches
the first semiconductor region (n- -type epitaxial layer EP) including a first portion (cell region CE) and a second portion (outer peripheral region EE + gate lead-out region DE) located around (FIG. 2A) the first portion along a plane (extending in x and y directions) that is perpendicular to a first direction (z-direction) from the first electrode (back electrode BE) to the first semiconductor region;
a first gate electrode portion (gate electrode GE, embedded in gate trench TRg) located on the first portion (cell region CE), and
a first wiring portion (termination trench TRe) located on the second portion (outer peripheral region EE + gate lead-out region DE).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have supplied the first portion and second portion of Tokuda to the semiconductor device of Yamamoto. Both Yamamoto et al. and Tokuda disclose vertical trench-gate power MOSFETs with similar objectives in reliable gate electrode structures. Yamamoto, however, does not disclose how the array terminates at the die edge. Whereas, Tokuda explicitly discloses a cell region bounded by gate lead-out region and outer peripheral region containing termination trench to relax electric field strength and route gate signal to the pad, and thus, supplies a known, conventional solution to the gap in Yamamoto et al. The termination architecture of Tokuda works in any cell design, so combination with the semiconductor device of Yamamoto et al. would work the same predictable way.
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FIG. 1 of Yamamoto et al., first annotation
Regarding claim 2, Yamamoto et al. in view of Tokuda teaches the semiconductor device according to claim 1. Yamamoto et al. teaches wherein
the conductor (gate electrode layer 10) includes an intermediate portion (see fifth annotated FIG. 1) located between the first connection portion, the second connection portion, and the end portion of the first wiring portion, and
a lower end (see fifth annotated FIG. 1) of the intermediate portion is positioned lower than a lower end (see fifth annotated FIG. 1) of the first wiring portion.
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FIG. 1 of Yamamoto et al., fifth annotation
Regarding claim 3, Yamamoto et al. in view of Tokuda teaches the semiconductor device according to claim 1. Yamamoto et al. teaches wherein
the first connection portion (see first annotated FIG. 1) has a first inclined surface (second annotated FIG. 1, side S2) that is inclined with respect to the second direction (y-direction) and the third direction (x-direction),
the second connection portion (see first annotated FIG. 1) has a second inclined surface (second annotated FIG. 1, side S3) that is inclined with respect to the second direction and the third direction,
the second inclined surface is continuous (FIG. 1) with the first inclined surface, and
an angle (second annotated FIG. 1, 120 degrees) between the first inclined surface and the second inclined surface is greater than 90 degrees and less than 150 degrees.
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FIG. 1 of Yamamoto et al., second annotation
Regarding claim 4, as best understood based on the 35 U.S.C. 112(b) issue identified above, Yamamoto et al. in view of Tokuda teaches the semiconductor device according to claim 1. Yamamoto et al. teaches wherein
the insulating layer (gate oxide film 9) includes
a first insulating region (see annotated sixth FIG. 1, corresponds to thin oxide on sidewalls (along 7a)) located between the end portion of the first wiring portion and the second portion (not explicitly disclosed), and
a second insulating region (see annotated sixth FIG. 1, corresponds to thick trench bottom (along 7b)) located between another end portion (see annotated sixth FIG. 1) in the
a thickness of the second insulating region is greater than ((24) and (9): side face 7a thin, bottom face 7b thick, where 7a perpendicular to and 7b parallel with layer 3 surface) a thickness of the first insulating region.
Yamamoto et al. does not explicitly teach a second portion. But Tokuda teaches the second portion (outer peripheral region EE + gate lead-out region DE).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have supplied the second portion of Tokuda to the semiconductor device of Yamamoto. Both Yamamoto et al. and Tokuda disclose vertical trench-gate power MOSFETs with similar objectives in reliable gate electrode structures. Yamamoto, however, does not disclose how the array terminates at the die edge. Whereas, Tokuda explicitly discloses a cell region bounded by gate lead-out region and outer peripheral region containing termination trench to relax electric field strength and route gate signal to the pad, and thus, supplies a known, conventional solution to the gap in Yamamoto et al. The region split taught in Tokuda supplies the structural frame, so combination with the semiconductor device of Yamamoto et al. would still work the same predictable way.
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FIG. 1 of Yamamoto et al., sixth annotation
Regarding claim 5, Yamamoto et al. in view of Tokuda teaches the semiconductor device according to claim 1. Yamamoto et al. does not teach wherein a length in the second direction of the first wiring portion is greater than a length in the second direction of the first gate electrode portion and greater than a length in the second direction of the second gate electrode portion.
However, Tokuda teaches wherein
a length (width W2) in the second direction (y-direction) of the first wiring portion ((31), termination trench TRe in region EE) is greater than (FIG. 5A and (33): W1<W2) a length (width W1) in the second direction of the first gate electrode portion ((28), gate trench TRg in cell region CE) and greater than a length (width W1) in the second direction of the second gate electrode portion ((28) and FIG. 4B, another TRg adjacent in y-direction).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have supplied the first portion and second portion of Tokuda to the semiconductor device of Yamamoto. While Yamamoto et al. and Tokuda both disclose vertical trench-gate power MOSFETs with similar objectives in reliable gate electrode structures, Yamamoto does not disclose how the array terminates at the die edge. However, Tokuda discloses a cell region bounded by gate lead-out region and outer peripheral region containing termination trench to relax electric field strength and route gate signal to the pad, and thus, supplies a known, conventional solution to the gap in Yamamoto et al. The termination architecture of Tokuda works in any cell design, so combination with the semiconductor device of Yamamoto et al. would work the same predictable way. In addition, Tokuda discloses a wider trench width W2 than W1 to ensure enough space for forming contact, which would also predictably provide similar benefit, of providing greater margin for gate contact where signal is picked off, to the densely packed array structure of Yamamoto.
Regarding claim 6, Yamamoto et al. in view of Tokuda teaches the semiconductor device according to claim 1. Yamamoto et al. teaches wherein
the second semiconductor region (p-type epitaxial layer 3) has a first surface (see fourth annotated FIG. 1) facing the first gate electrode portion (see fourth annotated FIG. 1) in the second direction (y-direction),
a crystal orientation of the first surface is {100} plane (cut along y-axis, parallel to x- and z-axes), and
a crystal orientation ({1120} face) of each of the inclined surfaces (sides S2 and S3) are inclined ((36), side face 7a smooth curved surface and (20), side face 7a of the trench 7 parallel with [1100] direction) with respect to the {100} plane and the {110} plane ((27), six faces listed are not parallel to either set, so inclined to both).
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FIG. 1 of Yamamoto et al., fourth annotation
Regarding claim 7, Yamamoto et al. in view of Tokuda teaches the semiconductor device according to claim 1. Yamamoto et al. teaches wherein
the conductor (gate electrode layer 10) further includes
a third gate electrode portion (see third annotated FIG. 1, following pattern of embodiment) extending in the third direction (x-direction), another second semiconductor region (p-type epitaxial layer 3) being located between the second gate electrode portion (see third annotated FIG. 1) and the third gate electrode portion,
a second wiring portion (see third annotated FIG. 1),
a third connection portion (see third annotated FIG. 1) located between the second end portion (see third annotated FIG. 1) and an end portion (see third annotated FIG. 1) in the third direction on of the second wiring portion, and
a fourth connection portion (see third annotated FIG. 1, following pattern of embodiment) located between a third end portion (see third annotated FIG. 1, following pattern of embodiment) in the third direction of the third gate electrode portion and the end portion of the second wiring portion,
a position (see third annotated FIG. 1, labeled “Pos 4”) in the second direction (y-direction) of the second wiring portion is between a position (see third annotated FIG. 1, labeled “Pos 3”) in the second direction of the second gate electrode portion and a position (see third annotated FIG. 1, labeled “Pos 5”) in the second direction of the third gate electrode portion, and
the third connection portion and the fourth connection portion have inclined surfaces (sides S5 and S6, respectively) that are inclined ((36), side face 7a smooth curved surface and (20), side face 7a of the trench 7 parallel with [1100] direction) with respect to the second direction and the third direction.
Yamamoto et al. does not explicitly teach a second portion. But Tokuda teaches wherein
second wiring portion ((31), termination trench TRe) located on the second portion (outer peripheral region EE + gate lead-out region DE).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have supplied the second portion of Tokuda to the semiconductor device of Yamamoto. Both Yamamoto et al. and Tokuda disclose vertical trench-gate power MOSFETs with similar objectives in reliable gate electrode structures. Yamamoto, however, does not disclose how the array terminates at the die edge. Whereas, Tokuda explicitly discloses a cell region bounded by gate lead-out region and outer peripheral region containing termination trench to relax electric field strength and route gate signal to the pad, and thus, supplies a known, conventional solution to the gap in Yamamoto et al. The termination architecture of Tokuda works in any cell design, so combination with the semiconductor device of Yamamoto et al. would work the same predictable way. In addition, Tokuda discloses multiple gate trenches and lead-out trenches, so extending the structural unit to include additional wiring portions yields similar results in a predictable way, following repeated structure.
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FIG. 1 of Yamamoto et al., third annotation
Regarding claim 8, Yamamoto et al. in view of Tokuda teaches the semiconductor device according to claim 1. Yamamoto et al. teaches wherein
a plurality of gate electrode portions (see FIG. 1) including the first gate electrode portion (see first annotated FIG. 1) and the second gate electrode portion (see first annotated FIG. 1) are arranged in the second direction (y-direction), and
a plurality of wiring portions (see FIG. 1) including the first wiring portion (see first annotated FIG. 1) are arranged in the second direction.
Yamamoto et al. does not explicitly teach a first portion and second portion. However, Tokuda teaches wherein
a plurality of gate electrode portions (FIG. 4B, gate electrodes GE, embedded in gate trench TRg) are arranged in the second direction (y-direction) on the first portion (cell region CE), and
a plurality of wiring portions (FIG. 4A, embedded electrode VE in termination trench TRe and lead-out electrode TE in lead-out trench TRd) are arranged in the second direction on the second portion (outer peripheral region EE + gate lead-out region DE).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have supplied the second portion of Tokuda to the semiconductor device of Yamamoto. Both Yamamoto et al. and Tokuda disclose vertical trench-gate power MOSFETs with similar objectives in reliable gate electrode structures. Yamamoto, however, does not disclose how the array terminates at the die edge. Whereas, Tokuda explicitly discloses a cell region bounded by gate lead-out region and outer peripheral region containing termination trench to relax electric field strength and route gate signal to the pad, and thus, supplies a known, conventional solution to the gap in Yamamoto et al. The termination architecture of Tokuda works in any cell design, so combination with the semiconductor device of Yamamoto et al. would work the same predictable way. In addition, Tokuda discloses multiple gate trenches and lead-out trenches, so extending the structural unit to include additional wiring portions yields similar results in a predictable way, following repeated structure.
Regarding claim 9, Yamamoto et al. in view of Tokuda teaches the semiconductor device according to claim 8. Yamamoto et al. teaches wherein
when viewed from the third direction (z-direction), the plurality of gate electrode portions (see FIG. 1) and the plurality of wiring portions (see FIG. 1) are alternately arranged (FIG. 1) in the second direction (y-direction).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEANNE M KIM whose telephone number is (571)272-8768. The examiner can normally be reached Monday-Thursday 8:00-6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JEANNE MYON KIM/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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