DETAILED ACTION
This action is responsive to the application filed 27 Sep 2024 and the Information Disclosure Statement filed 27 Sep 2024. Claims 1-15 are pending. Claim 1 is independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Notice of Foreign Priority Claim
Acknowledgment is made of applicant’s claim for foreign priority. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 27 Sep 2024 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Application Title
In accordance with MPEP 606.01 and MPEP 1302.04(a) to improve the descriptive nature of the application. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested:
“SENSING CIRCUIT FOR SWITCHED MAGNETORESISTIVE MEMORY ELEMENT”
No action is required by the applicant. If an allowance is processed, the Examiner will change the name as part of the Examiner’s Amendment process.
Examiner Note
The present application has used the limitation of “comprising”. The examiner notes that MPEP 2111.03 states, “The transitional term “comprising”, which is synonymous with “including,” “containing,” or “characterized by,” is inclusive or open-ended and does not exclude additional, unrecited elements or method steps.” The MPEP 2111.03 later states, “The transitional phrase “consisting of” excludes any element, step, or ingredient not specified in the claim.
Allowable Subject Matter
Claims 4 – 6, 11-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 2, 14, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Katayama, et al, U.S. Patent Application Publication 2022/0293155 (“Katayama”).
Regarding claim 1, Katayama teaches:
A storage device comprising: a first wiring extending in a first direction; a second wiring extending in a second direction intersecting the first direction; (Katayama, fig 6, 2A/B, “[0035] As shown in FIG. 6, one end of a switch circuit 61 and one end of a switch circuit 62 are connected to each word line 10, a global word line 63 is connected to the other end of the switch circuit 61, One end of a switch circuit 71 and one end of a switch circuit 72 are connected to each bit line 20, a global bit line 73 is connected to the other end of the switch circuit 71,”; a typical MTJ memory array with bit lines 20 (i.e. first wiring) in a “first direction” and word lines 10 (i.e. second wiring) in a “second direction”. Note, in Katayama, fig 6 the BLs and WLs both extend in a first and second direction; in fig 2B, they BL and WL extend in orthogonal directions, but also extend in the up/down third direction).
a memory cell provided between the first wiring and the second wiring, the memory cell including a resistance change storage element configured in a first resistance state or a second resistance state, and … the memory cell configured to store data based on a resistance state of the resistance change storage element; (Katayama, fig 2A/B, “[0021] The word lines 10 and the bit lines 20 each supply a predetermined signal to each memory cell 30 when data is written to or read from the memory cell 30. [0022] Each memory cell 30 includes a magnetoresistive effect element 40 that is a variable resistance memory element, and a selector, i.e., switching element 50 connected in series to the magnetoresistive effect element 40 for selecting the magnetoresistive effect element 40. [0027] the magnetoresistive effect element 40 is capable of storing binary data in response to the resistance state (low resistance state or high resistance state).”; a memory cell attached to the WL 10 and BL 20; each cell with an MTJ element 40; the MTJ stores data in a high or low resistance state; each cell with a selecting element 50 connected in series with 40).
a selector connected in series to the resistance change storage element and configured to shift from off-state to on-state when voltage higher than a first threshold voltage is applied, … (Katayama, fig 2A/B, 3, 4, “[0030] The selector 50… is a two terminal switching element that exhibits nonlinear current voltage characteristics. The selector 50 is set into a high resistance state, e.g., an electrically non-conductive state when a voltage applied across two terminals is lower than a threshold voltage, and is set into a low resistance state, e.g., an electrically conductive state when the voltage applied across the two terminals is equal to or higher than the threshold voltage.”; a selector 50 which shifts from on to off when a threshold voltage is applied).
a switching element configured to input a first signal from the second wiring and output a second signal to a third wiring different from the first wiring and the second wiring; (Katayama, fig 6, 7A/B/C, 8A/B/C, “[0030] The selector 50 is set into a high resistance state, e.g., an electrically non-conductive state when a voltage applied across two terminals is lower than a threshold voltage, and is set into a low resistance state, e.g., an electrically conductive state when the voltage applied across the two terminals is equal to or higher than the threshold voltage. [0047] It is noted that timing at which the read enable signal REN transitions to the high level does not necessarily match timing at which discharging of the selected bit line 20 starts, and the read enable signal REN may transition into the high level before the detection circuit 300 actually detects the data stored in the magnetoresistive effect element 40.”; that the WL (i.e. second wiring) apply a voltage above a threshold (i.e. first signal) to switch selector 50; paragraphs 0033- 0054 which describe fig 7A/B/C circuit 300 timing which show the resulting signal sent beyond the BL (i.e. first wiring) to the SA 320 (i.e. third wiring through transistors 81/82); fig 6 which describes a detection circuit 300 with an input from the bit line that provides an output from Sense Amplifier 320).
a voltage application circuit configured to apply a first voltage to the first wiring at a first time point such that a voltage higher than the first threshold voltage is applied to the selector; and (Katayama, fig 7A/B/C, 8A/B/C, “[0037] The detection circuit 300 includes a constant-current source 310 and a sense amplifier (S/A) 320, and a read enable transistor 81 and a clamp transistor 82 are connected between the detection circuit 300 and the global word line 63. [0038] The read operation will be specifically described hereinafter with reference to FIGS. 7A to 7C. FIG. 7A shows a voltage VGWL of the global word line 63 and a voltage VGBL of the global bit line 73. [0044] Specifically, at a time t2, the global word line control circuit 210 sets the global word line 63 into a floating state and the global bit line control circuit 220 sets the global bit line 73 into a floating state. [0049] When the voltage of the global word line 63 falls, the voltage difference between the voltage of the global word line 63 and the voltage of the global bit line 73 (such difference being equal to the voltage difference between the voltage of the selected word line 10 and the voltage of the selected bit line 20) reaches the hold voltage Vhold, that is, the voltage applied to the selected memory cell 30 reaches the hold voltage Vhold at a time t5.”; a voltage is applied to both the WL (i.e. second wiring) and BL (i.e. first wiring) such that the Vhold exceeds the (i.e. threshold voltage) for that memory cell after time t2 when the WL and BL are allowed to float and the results sent to the SA 320 (i.e. third wiring)).
a determination circuit configured to determine the resistance state of the resistance change storage element based on the second signal output to the third wiring at a second time point after the first time point. (Katayama, fig 7A/B/C, 8A/B/C, “[0051] Therefore, the detection circuit 300 including the sense amplifier 320 detects the resistance state of the magnetoresistive effect element 40 on the basis of the on-current that passes through the selector 50”; after t5, the detection circuit 300 uses SA 320 to determines the resistance state of the memory cell).
Regarding claim 2, Katayama teaches The storage device according to claim 1, wherein a potential of the first signal decreases or increases after the first time point, the determination circuit is configured to determine the resistance state of the resistance change storage element based on a potential at the second time point of the second signal depending on the potential of the first signal. (Katayama, fig 7A/B/C, 8A/B/C, “[0044] Specifically, at a time t2, the global word line control circuit 210 sets the global word line 63 into a floating state and the global bit line control circuit 220 sets the global bit line 73 into a floating state. [0049] When the voltage of the global word line 63 falls, the voltage difference between the voltage of the global word line 63 and the voltage of the global bit line 73 … reaches the hold voltage Vhold, that is, the voltage applied to the selected memory cell 30 reaches the hold voltage Vhold at a time t5. [0051] Specifically, the sense amplifier 320 detects the cell current Icell that passes through the selected memory cell 30, thereby determining the data stored in the magnetoresistive effect element 40.”; a description of the WL floating (i.e. falling) at t2 (i.e. first time point) and the measurement of the memory cell at t5 based on Vhold and then determines the state using Ihold1/2 using SA 320).
Regarding claim 14, Katayama teaches The storage device according to claim 1, wherein the resistance change storage element and the selector are stacked in a third direction intersecting the first direction and the second direction. (Katayama, fig 2A/B, “[0019] The memory cell array section 100 includes a plurality of word lines (also referred to herein as first interconnections) 10 that are provided on a base region, not shown, including a semiconductor substrate, not shown, and that extend in an X direction, a plurality of bit lines (also referred to herein as second interconnections) 20 that extend in a Y direction, and a plurality of memory cells 30 connected between the plurality of word lines 10 and the plurality of bit lines 20.”; that the BL and WL can be orthogonal and connected to the memory cell components 40-50 in the third dimension).
Regarding claim 15, Katayama teaches The storage device according to claim 1, wherein the resistance change storage element is a magnetoresistive effect element. (Katayama, fig 2A/B, “[0021] The word lines 10 and the bit lines 20 each supply a predetermined signal to each memory cell 30 when data is written to or read from the memory cell 30. [0022] Each memory cell 30 includes a magnetoresistive effect element 40 that is a variable resistance memory element, and a selector, i.e., switching element 50 connected in series to the magnetoresistive effect element 40 for selecting the magnetoresistive effect element 40. [0027] the magnetoresistive effect element 40 is capable of storing binary data in response to the resistance state (low resistance state or high resistance state).”; a memory cell attached to the WL 10 and BL 20; each cell with an MTJ element 40; the MTJ is a magnetoresistive element 40).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 3 and 7 – 10 are rejected under 35 U.S.C. 103 as being unpatentable over Katayama in view of Lam, et al, U.S. Patent Application Publication 2012/0063195 (“Lam”).
Regarding claim 3, Katayama teaches the storage device according to claim 2.
Katayama teaches wherein the determination circuit is configured to determine the resistance state of the resistance change storage element (Katayama, fig 7A/B/C, 8A/B/C, “[0044] Specifically, at a time t2, the global word line control circuit 210 sets the global word line 63 into a floating state and the global bit line control circuit 220 sets the global bit line 73 into a floating state. [0049] When the voltage of the global word line 63 falls, the voltage difference between the voltage of the global word line 63 and the voltage of the global bit line 73 … reaches the hold voltage Vhold, that is, the voltage applied to the selected memory cell 30 reaches the hold voltage Vhold at a time t5. [0051] Specifically, the sense amplifier 320 detects the cell current Icell that passes through the selected memory cell 30, thereby determining the data stored in the magnetoresistive effect element 40.”; a description of the WL floating (i.e. falling) at t2 (i.e. first time point) and the measurement of the memory cell at t5 based on Vhold and then determines the state using Ihold1/2 using SA 320).
Katayama does not explicitly teach by comparing the potential of the second signal at the second time point with a reference potential..
Lam teaches by comparing the potential of the second signal at the second time point with a reference potential. (Lam, fig 5, “[0053] The illustrative sense circuit 500 preferably comprises four basic building blocks: a reference generator 502; an MLC signal monitor 504; comparison circuitry 506; and time evaluation and storage circuitry 508. … The parameter being monitored may include various characteristics associated with the cell, such as, but not limited to, cell voltage, current, resistance, RC timing, etc., of the cell, as previously stated.”; a reference voltage (i.e. potential), current, resistance or RC timing can be used at the input of a SA to determine the memory cell state).
In view of the teachings of Lam it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lam to Katayama before the effective filing date of the claimed invention in order to teach magnetoresistive memory cell operation. The teachings of Lam, in the same or in a similar field of endeavor with Katayama, can combine Lam’s state determination using a reference and Katayama’s measurement to determine state. The slightly differing methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 7, Katayama teaches the storage device according to claim 1.
Katayama does not explicitly teach further comprising: a capacitor coupled to the third wiring..
Lam teaches further comprising: a capacitor coupled to the third wiring. (Lam, fig 5, “[0039] For example, in other embodiments, the measured parameter may be current, voltage, timing (e.g., resistor-capacitor (RC) timing), etc., associated with the memory cell.”; that line capacitance can be used to measure the state of the memory. Note: applicants specification (i.e. 0038) states that the “third wire” itself has an inherent, parasitic capacitance).
In view of the teachings of Lam it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lam to Katayama before the effective filing date of the claimed invention in order to teach magnetoresistive memory cell operation. The teachings of Lam, in the same or in a similar field of endeavor with Katayama, can combine Lam’s state resistor - capacitor determination as a state indication and Katayama’s measurement to determine state. The slightly differing methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 8, Katayama teaches the storage device according to claim 1.
Katayama does not explicitly teach wherein the switching element is a metal oxide semiconductor (MOS) transistor including a gate terminal, a first terminal corresponding to one terminal of a source terminal and a drain terminal, a second terminal corresponding to the other terminal of a source terminal and a drain terminal, and the first signal is input to the gate terminal and the second signal is output from the second terminal..
Lam teaches wherein the switching element is a metal oxide semiconductor (MOS) transistor including a gate terminal, a first terminal corresponding to one terminal of a source terminal and a drain terminal, a second terminal corresponding to the other terminal of a source terminal and a drain terminal, and the first signal is input to the gate terminal and the second signal is output from the second terminal. (Lam, fig 2, “[0031] FIG. 2 is a schematic diagram… [0032] Memory cell 200 is preferably configured such that a first terminal of the storage element connected with a corresponding bit line (BL) and a second terminal of the storage element is connected with the access device 204, such as a drain (D) of an NMOS transistor device as shown.”; that the switching device can be a NMOS, that the WL is connected to the gate, the signal, which represents BL current flow passes the source and drain of the NMOS).
In view of the teachings of Lam it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lam to Katayama before the effective filing date of the claimed invention in order to teach magnetoresistive memory cell operation. The teachings of Lam, in the same or in a similar field of endeavor with Katayama, can combine Lam’s NMOS switching element and Katayama’s switching element to determine memory state. The slightly differing methods merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 9, Katayama, as modified by Lam, teaches the storage device according to claim 8.
Katayama further teaches wherein the voltage application circuit is configured to change voltage of the first terminal at a time point before the second time point. (Katayama, fig 7A/B/C, 8A/B/C, “ [0038] The read operation will be specifically described hereinafter with reference to FIGS. 7A to 7C. FIG. 7A shows a voltage VGWL of the global word line 63 and a voltage VGBL of the global bit line 73. [0044] Specifically, at a time t2, the global word line control circuit 210 sets the global word line 63 into a floating state and the global bit line control circuit 220 sets the global bit line 73 into a floating state. [0049] When the voltage of the global word line 63 falls, the voltage difference between the voltage of the global word line 63 and the voltage of the global bit line 73 (such difference being equal to the voltage difference between the voltage of the selected word line 10 and the voltage of the selected bit line 20) reaches the hold voltage Vhold, that is, the voltage applied to the selected memory cell 30 reaches the hold voltage Vhold at a time t5.”; paragraph 0033- 0054 which describe fig 7A/B/C circuit 300 timing; fig 6 which describes a detection circuit 300 with an input from the bit line that provides an output from Sense Amplifier 320; that the BL and WL voltages are configured to float (i.e. change voltage) at time t2).
Regarding claim 10, Katayama, as modified by Lam, teaches the storage device according to claim 9.
Katayama further teaches wherein a time point when the voltage application circuit changes the voltage of the first terminal is synchronized with the first time point. (Katayama, fig 7A/B/C, 8A/B/C, “ [0038] The read operation will be specifically described hereinafter with reference to FIGS. 7A to 7C. FIG. 7A shows a voltage VGWL of the global word line 63 and a voltage VGBL of the global bit line 73. [0044] Specifically, at a time t2, the global word line control circuit 210 sets the global word line 63 into a floating state and the global bit line control circuit 220 sets the global bit line 73 into a floating state. [0049] When the voltage of the global word line 63 falls, the voltage difference between the voltage of the global word line 63 and the voltage of the global bit line 73 (such difference being equal to the voltage difference between the voltage of the selected word line 10 and the voltage of the selected bit line 20) reaches the hold voltage Vhold, that is, the voltage applied to the selected memory cell 30 reaches the hold voltage Vhold at a time t5.”; paragraph 0033- 0054 which describe fig 7A/B/C circuit 300 timing; fig 6 which describes a detection circuit 300 with an input from the bit line that provides an output from Sense Amplifier 320; that the BL and WL voltages are configured to float (i.e. change voltage) at time t2).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONALD H.B. BRASWELL whose telephone number is (469)295-9119. The examiner can normally be reached on 7-5 Central Time (Dallas).
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825
Prosecution Insights