Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1, 11 and 16
b. Pending: 1-20
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) are submitted on 8/27/2024 and 4/15/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 11 is objected to because of the following informalities: it misses a punctuation mark (line: 6), at the end of sentence: “wherein the first and second memory cells are divided into a plurality of active blocks” Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20220263408) in view of Lee et al. (US 20020093869).
Regarding independent claim 1, Hong discloses a memory device (Fig. 11 and [0151] describes that semiconductor device 8 is a memory device (e.g., a nonvolatile memory device), the internal circuit 83 may include a word line driver that operates using a high voltage) comprising:
a memory cell array having a plurality of active blocks, each of the plurality of active blocks including a plurality of memory cells being configured to operate at a clock frequency;
a voltage generator configured to provide an operating voltage to the plurality of memory cells (Fig. 11; dashed block 81); and
a control logic configured to control an independent memory operation for each of the plurality of active blocks (Fig. 11; within blocks 812 and 814 there are control logic to perform memory operation via internal circuit 83) ,
wherein the voltage generator includes a pump circuit (Fig. 11 shows that block 81 includes first charge pump block 4, first pump control signal generation block 5 and clock generation block 6) configured to change the clock frequency ([0088] describes clock generation block 6 may change the frequency of the operation clock CLK according to the number of activated signals among the N first pump control signals STG<1:N> generated by the first pump control signal generation block 5) and generate the operating voltage according to a number of active blocks activated during the independent memory operation ([0032] describes first pump control signal generator suitable to selectively activate the pump control signals corresponding to a target level of the pumping voltage; and a clock generator suitable to change a frequency of the operation clock based on a number of the activated pump control signals).
Hong doesn’t disclose a memory cell array having a plurality of active blocks, each of the plurality of active blocks including a plurality of memory cells being configured to operate at a clock frequency;
However, Lee teaches a memory cell array having a plurality of active blocks, each of the plurality of active blocks including a plurality of memory cells being configured to operate at a clock frequency ([0026], [0064] describes a multi-bank semiconductor memory device that is capable of varying a driving capability of a voltage generator according to the number of active banks);
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Lee to Hong in order to provide optimized power consumption by varying the number of active driving circuits according to the number of active banks as taught by Lee ([0029]).
Regarding claim 2, Hong and Lee together disclose all the elements of claim 1 as above and through Lee further the independent memory operation is a read operation or a program operation independently performed between activated active blocks ([0013] describes reading/writing operations of memory 10).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Lee to modified Hong in order to provide optimized power consumption by varying the number of active driving circuits according to the number of active banks as taught by Lee ([0029]).
Regarding claim 3, Hong and Lee together disclose all the elements of claim 1 as above and through Hong further the independent memory operation is an erase operation performed independently between activated active blocks ([0003] describes that during operation of a semiconductor device (e.g., flash memory, EEPROM, DRAM), a voltage in a certain range may be used, for example, to perform a program operation and/or erase operation).
Regarding claim 4, Hong and Lee together disclose all the elements of claim 1 as above and further the plurality of active blocks are mats, and each of the mats includes a plurality of memory cells being configured to operate at the clock frequency (here examiner asserts that blocks, banks, mats etc., are all interchangeable terms).
Regarding claim 5, Hong and Lee together disclose all the elements of claim 1 as above and through Hong further the pump circuit comprises: a mode selector configured to receive an active block use signal and a mode selection signal from the control logic and select one of a plurality of modes; and a clock generator configured to change the clock frequency in response to a mode signal selected by the mode selector ([0066] and [0088] describes operation signals STAGE_UP, STAGE_DN and PUMP_EN may be generated by a mode register set (MRS) in the semiconductor device. And clock generation signal OCS_EN may be generated by a mode register set (MRS) in the semiconductor device).
Claims 8 are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20220263408) in view of Lee et al. (US 20020093869) and Dick (US 20140050286).
Regarding claim 8, Hong and Lee together disclose all the elements of claim 5 as above and through Dick further the mode selection signal is provided from a pump scheduler of a memory controller (Fig. 2 shows scheduler 230 provides output to two different units 221 and 222 (operate in two modes)).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Dick to modified Hong in order to provide either an indication of first scheduling information or second scheduling information to the first estimation unit and the second estimation unit as taught by Dick ([0005]).
Claims 16-20 recite limitation for claims 1-5 and 8 in method format and henceforth rejected the same way.
Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20220263408) in view of Lee et al. (US 20020093869) and Asami et al. (US 20160259576).
Regarding independent claim 11, Asami discloses a memory device (Figs. 1-5) comprising:
a first stack in which first memory cells are stacked in a direction perpendicular to a substrate (Fig. 4 and [0053]-[0055] describes substrate 20 and that memory cells are stacked in a perpendicular direction over 20); and
a second stack in which second memory cells are stacked on the first stack in a direction perpendicular to the substrate (Fig. 4 and [0053]-[0055]),
wherein the first and second memory cells are divided into a plurality of active blocks ((Fig. 2 and [0036] describes four blocks BLK (BLK0 to BLK3) each of which is a set of nonvolatile memory cells)
Remaining part of claim 11 recites same claim limitations from independent device claim 1 in method format and henceforth rejected the same way.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Lee to Hong in order to provide optimized power consumption by varying the number of active driving circuits according to the number of active banks as taught by Lee ([0029]) and to provide with mechanism for storing fixation failure string position information in memory hole units (memory string units) as taught by Asami ([0026]) respectively.
Claims 12-15 recites same claim limitations of device claims 2-5 and 8 in method format and henceforth rejected same way.
Allowable Subject Matter
Claims 6-7 and 9-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SULTANA BEGUM whose telephone number is (571)431-0691. The examiner can normally be reached M-F 8 am - 5 pm.
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 3/5/2026