DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
The drawings are objected to because the written specification states a recess 11 and a mesa 10 however in the figures it appears that 10 is mistakenly pointing at the recess and 11 at the mesa. This is further evidenced by the recess expose portions 14 and the through hole along the surface of the mesa 13 pointing to swapped sides.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation “a plurality of sub-through holes and a central through hole, wherein each of the plurality of sub-through holes is uniformly distributed around the central through hole.” Of claim 5 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xiaoliang Liu (US 20210066549 A1) Hereinafter referred to as “Liu”.
Regarding Claim 1 Liu teaches
An LED chip (Fig 11), comprising:
a substrate (110);
an epitaxial stack (120), provided on a surface of the substrate, comprising a recess (1211) and a mesa (Fig 11 portion of epitaxial stack above the recess);
an isolating layer (141), covering the epitaxial stack (120) and exposing a portion of a surface of the recess (1211) to form a recess exposed portion, wherein the isolating layer (141) comprises at least one hole (162 see diagram) along a surface of the mesa (see diagram);
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a current spreading layer (130, 151, and 152), stacked on a side surface of the isolating layer (141), wherein the side surface is located away from (not in direct contact with) the mesa, and the current spreading layer is embedded in the at least one through hole to contact with the epitaxial stack;
a reflective layer (142 Para[0028],[0036]), covering the current spreading layer (130, 151, and 152) and the isolating layer(141), wherein the reflective layer (142) exposes (does not cover) the recess exposed portion (of the recess 1211 Fig 11) and comprises an electrode hole (has a hole for two electrodes 171 and 172 ), the electrode hole exposes a portion (Fig 11) of the current spreading layer (130, 151, and 152);
a first electrode (171), stacked on the recess exposed portion and extending upward to a surface of the reflective layer; and
a second electrode (172), stacked on the electrode hole and extending upward to the surface of the reflective layer.
Regarding Claim 2 Liu teaches
The LED chip (Fig 11) according to claim 1,
wherein the epitaxial stack (121, 122, 123) comprises a first type semiconductor layer (121), an active layer (122), and a second type semiconductor layer (123),
wherein the first type semiconductor layer, the active layer, and the second type semiconductor layer are sequentially stacked in a first direction (Fig 11),
a local area of the epitaxial stack is etched to a part of the first type semiconductor layer (121), forming the recess (1211) and the mesa, and the first direction is perpendicular to the substrate, and points from the substrate to the epitaxial stack.
Regarding Claim 3 Liu teaches
The LED chip according to claim 1,
wherein a total surface area of the at least one through hole (162 see diagram) is S, an area of a top surface of the mesa is A, and S ≥ A/5; (Para [0031] teaches S=A/2)
wherein the total surface area of the at least one through hole is a sum of at least one projected area of the at least one through hole on the top surface of the mesa. (Para [0031] teaches this limitation explicitly but also as a result effective variable)
Regarding Claim 4 Liu teaches
The LED chip according to claim 1,
wherein the at least one through hole (see diagram) does not overlap with the electrode hole in orthogonal projections onto the mesa. (Fig 11)
Regarding Claim 5 Liu teaches
The LED chip according to claim 1,
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wherein the at least one through hole comprises a plurality of sub-through holes and a central through hole, wherein each of the plurality of sub-through holes is uniformly distributed around the central through hole. (given the through hole of Liu, imagine splitting the hole into three even parts. This gives us a central and two surrounding sub-though holes with no intervening layers. See diagram)
Regarding Claim 6 Liu teaches
The LED chip according to claim 1, further comprises:
a current spreading metal layer (152) disposed on the current spreading layer (130, 151, 152), wherein the electrode hole exposes the current spreading metal layer to form a connection between the second electrode and the current spreading metal layer. (Fig 11)
Regarding Claim 7 Liu teaches
The LED chip according to claim 6,
the current spreading metal layer is made of any one or any combination of chromium, nickel, aluminum, titanium (Para [0033]), platinum, gold, palladium, silver, or a gold-tin alloy.
Regarding Claim 8 Liu teaches
The LED chip according to claim 1,
wherein a center of the electrode hole (center of 171 and/or 172) is not aligned (above) with a center of the at least one through hole. (Fig 11)
Regarding Claim 9 Liu teaches
The LED chip according to claim 1,
wherein the reflective layer (142) comprises a Distributed Bragg Reflector (DBR) reflective layer. (Para [0028],[0036])
Regarding Claim 10 Liu teaches
The LED chip according to claim 1,
wherein the current spreading layer (130, 151, 152) is made of any one or any combination of ITO, IZO, IGO, or ZnO, (Para [0026]) or wherein the first electrode or the second electrode is made of any one or any combination of chromium, nickel, aluminum, titanium, platinum, gold, palladium, silver, or a gold-tin alloy.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu and further in view of Feng Wang (US 20210119086 A1) hereinafter referred to as “Wang”
Regarding Claim 11 Liu teaches
The LED chip according to claim 1,
wherein the isolating layer (141) and the reflective layer (142) are stacked on the substrate
Liu is not relied upon to teach
wherein the epitaxial stack comprises at least one substrate exposed portion, the isolating layer and the reflective layer are stacked on the substrate by being retained on the at least one substrate exposed portion.
Wang teaches a similar stack
wherein the epitaxial stack (102, 103, 104) comprises at least one substrate exposed portion (Fig 4 Para [0027]), the isolating layer (109) and the reflective layer (106 Para [0030]) are stacked on the substrate by being retained on the at least one substrate exposed portion.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Liu such that there is at least one substrate exposed portion, as described in Wang because the modification allows for a cutting region for a cutting process wherein the epitaxial structure is still surrounded. (Wang Para [0027])
Regarding Claim 12 Liu in view of Wang teaches
The LED chip according to claim 11,
wherein the at least one substrate exposed portion surrounds a perimeter of the epitaxial stack (Wang Para [0027]), the isolating layer (Wang 109) and the reflective layer (Wang 106) are stacked on the substrate by being retained on the at least one substrate exposed portion and surrounding a perimeter of the epitaxial stack. (Wang Fig 4)
Regarding Claim 13 Liu teaches
A LED chip (Fig 11) preparation method comprising:
providing a substrate (110);
stacking an epitaxial stack (120) on a surface of the substrate;
etching a local area (Fig 2) of the epitaxial stack to form a recess (1211) and a mesa;
growing an isolating layer (141) which covers the epitaxial stack and exposes a portion of a surface of the recess to form a recess exposed portion, wherein the isolating layer comprises at least one through hole (162 see diagram) along a surface of the mesa;
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depositing a current spreading layer (130, 151, and 152) which is stacked on a side surface of the isolating layer (141), wherein the side surface is located away from (not in direct contact with) the mesa, and the current spreading layer is embedded in the at least one through hole to contact with the epitaxial stack;
depositing a reflective layer (142 Para[0028],[0036]) which covers the current spreading layer (130, 151, and 152) and the isolating layer (141), wherein the reflective layer (142)exposes the recess exposed portion (of the recess 1211 Fig 11) and comprises an electrode hole (has a hole for two electrodes 171 and 172 ), the electrode hole exposes a portion (Fig 11) of the current spreading layer; and
preparing a first electrode (171) and a second electrode (172), wherein the first electrode is stacked on the recess exposed portion, the second electrode is stacked in the electrode hole, and the first electrode and the second electrode are disposed away from each other.
Liu is not relied upon to teach
etching an edge of the epitaxial stack to form a substrate exposed portion;
Wang teaches
Etching (Fig 8-9 Para [0047]) an edge of the epitaxial stack to form a substrate exposed portion;
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Liu such that there is a substrate exposed portion, as described in Wang because the modification allows for a cutting region for a cutting process wherein the epitaxial structure is still surrounded. (Wang Para [0027])
Regarding claim 14 Liu in view of Wang teaches
The LED chip preparation method according to claim 13,
Liu further teaches
wherein a total surface area of the at least one through hole (162 see diagram) is S, an area of a top surface of the mesa is A, and S ≥ A/5; (Para [0031] teaches S=A/2)
wherein the total surface area of at least one through hole is a sum of at least one projected area of the at least one through hole on the top surface of the mesa. (Para [0031] teaches this limitation explicitly but also as a result effective variable)
Regarding Claim 15 Liu in view of Wang teaches
The LED chip preparation method according to claim 13,
Liu further teaches
wherein the epitaxial stack (121, 122, 123) comprises a first type semiconductor layer (121), an active layelayer (, and a second type semiconductor layer (123); wherein the first type semiconductor layer, the active layer, and the second type semiconductor layer are sequentially stacked in a first direction (Fig 11);
wherein the first direction is perpendicular to the substrate, and points from the substrate to the epitaxial stack;
wherein etching the local area (Fig 2) of the epitaxial stack to form the recess and the mesa comprises: etching the local area of the epitaxial stack to a part of the first type semiconductor layer (121) to form the recess and the mesa. (Fig 2 and 11)
Regarding Claim 16 Liu in view of Wang teaches
The LED chip preparation method according to claim 13, further comprising:
Liu further teaches
depositing a current spreading metal layer (152) on a surface of the current spreading layer (130, 151, 152) (Fig 8 and 11).
Regarding Claim 17 Liu in view of Wang teaches
The LED chip preparation method according to claim 13,
Liu further teaches
the current spreading metal layer (152) is made of any one or any combination of chromium, nickel, aluminum, titanium (Para [0033]), platinum, gold, palladium, silver, or a gold-tin alloy.
Regarding Claim 18 Liu in view of Wang teaches
The LED chip preparation method according to claim 13,
Liu further teaches
wherein a center of the electrode hole (center of 171 and/or 172) is not aligned (above) with a center of at least one through hole. (Fig 11)
Regarding Claim 19 Liu in view of Wang teaches
The LED chip preparation method according to claim 13,
Liu further teaches
wherein the reflective layer (142) comprises a DBR reflective layer. (Para [0028],[0036])
Regarding Claim 20 Liu in view of Wang teaches
The LED chip preparation method according to claim 13,
Liu further teaches
wherein the current spreading layer (130, 151, 152) is made of any one or any combination of ITO, IZO, IGO, or ZnO, (Para [0026]) or wherein the first electrode or the second electrode is made of any one or any combination of chromium, nickel, aluminum, titanium, platinum, gold, palladium, silver, or a gold-tin alloy.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. JIANG; Bin (US 20240322086 A1)
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/JAIME LYNN SPRENGER/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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