DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-20 are objected to because of the following informalities:
Claim 1 (claims 4, 8-9, and 11) recites “each of the dummy vertical structures” (lines 16 and 20) which should be replaced with “each of the plurality of dummy vertical structures”, to avoid antecedent basis issue.
Claim 6 (claims 7 and 10) recites “the dummy vertical structures” which should be replaced with “the plurality of dummy vertical structures”, to avoid antecedent basis issue.
Claim 12 (claims 13-14 and 16) recites “the ground selection gate patterns” (lines 12 and 15) which should be replaced with “the plurality of ground selection gate patterns”, to avoid antecedent basis issue.
Claim 12 recites “second separation structures” (line 14) which should be replaced with “the second separation structures””, to avoid antecedent basis issue.
Claim 13 (claims 15 and 19-20) recites “the cell gate patterns” which should be replaced with “the plurality of cell gate patterns”, to avoid antecedent basis issue.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention
Claim 1 recites limitations “the ground selection gate patterns” in line 19. There is insufficient antecedent basis for this limitation in the claim because it is unclear whether “the ground selection gate patterns” relates back to “a first ground selection gate pattern”, “ a second ground selection gate pattern” (recited in lines 13-14), “a plurality of ground selection gate patterns” (recited in line 3), or to set forth additional ground selection gate patterns.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2020/0303413 to Shin et al. (cited in IDS of 03/14/2025, hereinafter Shin).
With respect to claim 1, Shin discloses a semiconductor device (e.g., a semiconductor memory device) (Shin, Figs. 1, 3, 4A-4D, 5-6, 11, ¶0021-¶0073) comprising:
a substrate (101) (Shin, Figs. 1, 3, 4A-4D, ¶0033-¶0035) including a cell array region (I) and a connection region (II);
a plurality of ground selection gate patterns (e.g., gate electrode 131 used as a ground select line is divided into subgate electrodes 131a and 131b) (Shin, Figs. 1, 3, 4A-4D, 5, ¶0059) with each ground selection gate pattern spaced apart (e.g., by MS2 and GS) from each other and disposed at the same level as each other relative to a top surface of the substrate (101);
a plurality of cell gate patterns (e.g., a plurality of cell gate patterns 132-136 divided by isolation regions MS2) (Shin, Figs. 1, 3, 4A-4D, 5, ¶0036, ¶0056-¶0058) vertically stacked on the plurality of ground selection gate patterns (131a/131b);
a plurality of separation structures (e.g., isolation regions MS2 divided by the lower isolation region GS/GSa) (Shin, Figs. 3, 4A-4D, 5-6, ¶0037, ¶0050-¶0051, ¶0061), with each separation structure vertically extending into the cell gate patterns (132-136) and disposed between respective ground selection gate patterns (131a/131b) of the plurality of ground selection gate patterns and spaced apart from each other in a first direction (e.g., X-direction) in the connection region (II); and
a plurality of dummy vertical structures (e.g., a plurality of dummy channels DCH2a arranged in the X-direction and extending into the lower isolation region GSa, as in Fig. 6) (Shin, Figs. 3, 4C, 6, ¶0046-¶0047, ¶0053, ¶0061-¶0062) disposed between a first separation structure (e.g., MS2 at the right side of Fig. 6) and a second separation structure (e.g., MS2 at the left side of Fig. 6) that are adjacent in the first direction (e.g., the X-direction) and between a first ground selection gate pattern (131a) and a second ground selection gate pattern (131b) adjacent to the first ground selection gate pattern,
wherein each of the dummy vertical structures (e.g., the plurality of dummy channels DCH2a arranged in the X-direction and extending into the lower isolation region GSa, as in Fig. 6) (Shin, Figs. 3, 4C, 6, ¶0046-¶0047, ¶0053, ¶0061-¶0062) includes:
a vertical portion (e.g., channel portions 105/140/150) (Shin, Figs. 3,4C, 6, ¶0043, ¶0045, ¶0047, ¶0061) that extends vertically into the cell gate patterns (132-136); and
an extension (e.g., an insulation layer 170 of the isolation region GSa in Fig. 6) (Shin, Figs. 3,4C, 6, ¶0053, ¶0061-¶0062) that protrudes horizontally from the vertical portion (e.g., channel portions 105/140/150) at the same level as the ground selection gate patterns (131/131b), and
wherein the extension (e.g., an insulation layer 170 of the GS region) (Shin, Figs. 3, 4C, 6, ¶0053, ¶0061-¶0062) of each of the dummy vertical structures (e.g., DCH2a arranged in the X-direction and extending into the lower isolation region GSa, as in Fig. 6) are connected to each other and are in contact with the first separation structure (e.g., MS2 at the right side of Fig. 6) and the second separation structure (e.g., MS2 at the left side of Fig. 6).
Regarding claim 3, Shin discloses the semiconductor device of claim 1. Further, Shin discloses the semiconductor device, wherein each of the cell gate patterns (132-136) (Shin, Figs. 3, 4A-4D, 6, ¶0036, ¶0056-¶0058, ¶0061-¶0062) has a first thickness in a vertical direction, and each of the ground selection gate patterns (131) has a second thickness in the vertical direction that is equal to the first thickness.
Regarding claim 4, Shin discloses the semiconductor device of claim 1. Further, Shin discloses the semiconductor device, wherein a thickness in a vertical direction of the extension (170) (Shin, Figs. 3, 4C, 6, ¶0036, ¶0053, ¶0061-¶0062) of each of the dummy vertical structures (DCH2a) is the same as a thickness in the vertical direction of the ground selection gate patterns (131).
Regarding claim 5, Shin discloses the semiconductor device of claim 1. Further, Shin discloses the semiconductor device, wherein a distance between a first cell gate pattern (132) (Shin, Figs. 3, 4A-4D, 5, 6, ¶0036, ¶0052-¶0059, ¶0061-¶0062) and a second cell gate pattern (133) that is vertically adjacent to the first cell gate pattern is equal to a distance between the first cell gate pattern (132) and a ground selection gate pattern (131) that is vertically adjacent to the first cell gate pattern.
Regarding claim 6, Shin discloses the semiconductor device of claim 1. Further, Shin discloses the semiconductor device, wherein a distance between the first separation structure (e.g., MS2 at the right side of Fig. 6) (Shin, Fig. 6, ¶0061-¶0062) and the second separation structure (e.g., MS2 at the left side of Fig. 6) in the first direction (e.g., the X-direction) is greater than the sum of the diameters of the vertical portions of the dummy vertical structures (DCH2a).
Regarding claim 7, Shin discloses the semiconductor device of claim 1. Further, Shin discloses the semiconductor device, wherein the cell gate patterns (132-136) (Shin, Figs. 3, 4C, 6, ¶0036, ¶0053, ¶0061-¶0062) surround the vertical portions (140/150) of the dummy vertical structures in the connection region (II).
Regarding claim 8, Shin discloses the semiconductor device of claim 1. Further, Shin discloses the semiconductor device, wherein the cell gate patterns (132/136) overlap the extension (GS/GSa) (Shin, Figs. 3, 4A, 4C, 6, ¶0036, ¶0053, ¶0061-¶0062) of each of the dummy vertical structures (DCH2a).
Regarding claim 9, Shin discloses the semiconductor device of claim 1. Further, Shin discloses the semiconductor device, wherein sidewalls of the ground selection gate patterns (131) (Shin, Figs. 3, 4C, 4D, 6, ¶0033, ¶0036, ¶0053, ¶0061-¶0062) are in contact with the separation structures (MS2) (Shin, Fig. 4D) and the extension (GSa) (Shin, Fig. 4C) of each of the dummy vertical structures (e.g., DCH2a, arranged in the X-direction in Fig. 6).
Regarding claim 10, Shin discloses the semiconductor device of claim 1. Further, Shin discloses the semiconductor device, wherein the dummy vertical structures (e.g., DCH2a, arranged in the X-direction in Fig. 6) are formed of an insulating material (e.g., 150 and 170) (Shin, Figs. 3, 4A, 4C, 6, ¶0043, ¶0053, ¶0061-¶0062).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0303413 to Shin in view of Ha et al. (US 2018/0122742, hereinafter Ha).
Regarding claim 2, Shin discloses the semiconductor device of claim 1. Further, Shin does not specifically disclose the semiconductor device, wherein each of the cell gate patterns has a first thickness in a vertical direction, and each of the ground selection gate patterns has a second thickness in the vertical direction that is greater than the first thickness.
However, Ha teaches forming the semiconductor device (Ha, Fig. 3, ¶0026-¶0030) with enhanced reliability, wherein each of the cell gate patterns (120b) has a first thickness (T2) in a vertical direction, and each of the ground selection gate patterns (120a) has a second thickness (T1) in the vertical direction that is greater than the first thickness (T2), to have increased channel length and larger threshold voltage to provide memory string with increased current and improved current controllability (Ha, ¶0005, ¶0030).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Shin by forming the cell gate patterns and the ground selection gate patterns having specific thicknesses as taught by Ha to have the semiconductor device, wherein each of the cell gate patterns has a first thickness in a vertical direction, and each of the ground selection gate patterns has a second thickness in the vertical direction that is greater than the first thickness, in order to have increased channel length and larger threshold voltage to provide memory string with increased current and improved current controllability (Ha, ¶0005, ¶0030).
Claims 11-12 and 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0303413 to Shin in view of Lee (US 2020/0127126).
Regarding claim 11, Shin discloses the semiconductor device of claim 1. Further, Shin does not specifically disclose the semiconductor device, wherein each of the dummy vertical structures further includes cell extensions with each cell extension horizontally protruding from the vertical portion at the same level as a respective cell gate pattern, and wherein diameters of the cell extensions are smaller than diameters of the extension of each of the dummy vertical structures.
However, Lee teaches forming a semiconductor memory device (Lee, Fig. 3, 4A, 5A-5D, 6B, ¶0004, ¶0039-¶0096) with increased staking number of gates, wherein the memory device comprises dummy vertical structures (40d) (Lee, Fig. 3, 4A, 5A-5D, 6B, ¶0045, ¶0058, ¶0062-¶0068, ¶0095-¶0096) having the same structure as the memory vertical structures (40) and including an extension (e.g., horizontal portion of the dielectric layer 26) that protrudes horizontally from the vertical portion (e.g., insulating core 34) of each of the dummy vertical structures at the same level as a respective cell gate pattern (50) and at the same level as the ground selection gate patterns (e.g., the lower gate electrode 50L), to isolate data storage pattern, and to provide a semiconductor memory device with improved degree of integration.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Shin by forming each dummy vertical structure including an insulating extension layer as taught by Lee to have the semiconductor device, wherein each of the dummy vertical structures further includes cell extensions with each cell extension horizontally protruding from the vertical portion at the same level as a respective cell gate pattern, and wherein diameters of the cell extensions are smaller than diameters of the extension of each of the dummy vertical structures, in order to isolate data storage pattern, and to provide a semiconductor memory device with improved degree of integration (Lee, ¶0004, ¶0045, ¶0058, ¶0062-¶0065).
With respect to claim 12, Shin discloses a semiconductor device (e.g., a semiconductor memory device) (Shin, Figs. 1, 3, 4A-4D, 5-6, 11, ¶0021-¶0073) comprising:
a substrate (101) (Shin, Figs. 1, 3, 4A-4D, ¶0033-¶0035) including a cell array region (I) and a connection region (II);
first separation structures (MS1) (Shin, Figs. 1, 3, 4A-4D, 5, ¶0037) extending in a first direction (e.g., X-direction) parallel to a top surface of the substrate (101);
a stacked structure (120/130) (Shin, Figs. 1, 3, 4A-4D, 5, ¶0033) disposed between first separation structures (MS1) that are adjacent in a second direction (e.g., Y-direction) perpendicular to the first direction and including gate patterns (130) and interlayer insulating layers (120) alternately stacked vertically on the substrate (101), the gate patterns (130) including a plurality of ground selection gate patterns (e.g., gate electrode 131 used as a ground select line is divided into subgate electrodes 131a and 131b) (Shin, Figs. 1, 3, 4A-4D, 5, ¶0059) with each ground selection gate pattern spaced apart from each other at the same level from the top surface of the substrate (101), and a plurality of cell gate patterns (e.g., a plurality of cell gate patterns 132-136 divided by isolation regions MS2) (Shin, Figs. 1, 3, 4A-4D, 5, ¶0036, ¶0056-¶0058) vertically stacked on the plurality of ground selection gate patterns (131a/131b);
second separation structures (e.g., isolation regions MS2 divided by the lower isolation region GS/GSa) (Shin, Figs. 3, 4A-4D, 5-6, ¶0037, ¶0050-¶0051, ¶0061) extending into the plurality of cell gate patterns (132-136) and disposed between the ground selection gate patterns (131/131b) (Shin, Fig. 5) that are adjacent in the second direction (e.g., the Y-direction), and spaced apart from each other in the connection region (II) in the first direction (e.g., the X-direction);
first dummy vertical structures (e.g., a plurality of dummy channels DCH2a arranged in the X-direction and extending into the lower isolation region GSa, as in Fig. 6) (Shin, Figs. 3, 4C, 6, ¶0046-¶0047, ¶0053, ¶0061-¶0062) disposed between second separation structures (e.g., MS2 at the right side and the left side of Fig. 6) adjacent to each other in the first direction (e.g., the X-direction) and between the ground selection gate patterns (131a/131b) that are adjacent in the second direction (e.g., the Y-direction); and
second dummy vertical structures (DCH1) (Shin, Figs. 3, 4D, 6, ¶0046-¶0047, ¶0053, ¶0061-¶0062) extending into the stacked structure (120/130) in the connection region (II),
wherein each of the first and second dummy vertical structures (DCH2a and DCH1) includes a vertical portion (e.g., channel portions 105/140/150) (Shin, Figs. 3,4C, 6, ¶0043, ¶0045, ¶0047, ¶0061) that extends vertically into the cell gate patterns (132-136) and each of the first dummy vertical structures (DCH2a) incldues an extension (e.g., an insulation layer 170 of the isolation region GSa in Fig. 6) (Shin, Figs. 3,4C, 6, ¶0053, ¶0061-¶0062) that protrudes horizontally from the vertical portion at the same level as the ground selection gate patterns (131/13b), and
wherein each extension (e.g., an insulation layer 170 of the GS region) (Shin, Figs. 3, 4C, 6, ¶0053, ¶0061-¶0062) of the first dummy vertical structures (e.g., DCH2a arranged in the X-direction and extending into the lower isolation region GSa, as in Fig. 6) are connected to each other and are in contact with the second separation structures (e.g., MS2) that are adjacent to each other in the first direction (e.g., X-direction).
Further, Shin does not specifically disclose that each of the second dummy vertical structures includes an extension that protrudes horizontally from the vertical portion at the same level as the ground selection gate patterns.
However, Lee teaches forming a semiconductor memory device (Lee, Fig. 3, 4A, 5A-5D, 6B, ¶0004, ¶0039-¶0096) with increased staking number of gates, wherein the memory device comprises dummy vertical structures (40d) (Lee, Fig. 3, 4A, 5A-5D, 6B, ¶0045, ¶0058, ¶0062-¶0068, ¶0095-¶0096) having the same structure as the memory vertical structures (40) and including an extension (e.g., horizontal portion of the dielectric layer 26) that protrudes horizontally from the vertical portion (e.g., insulating core 34) of each of the dummy vertical structures at the same level as the ground selection gate patterns (e.g., the lower gate electrode 50L), to isolate data storage pattern, and to provide a semiconductor memory device with improved degree of integration.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Shin by forming each dummy vertical structure including an insulating extension layer as taught by Lee to have the semiconductor device, wherein each of the second dummy vertical structures includes an extension that protrudes horizontally from the vertical portion at the same level as the ground selection gate patterns, in order to isolate data storage pattern, and to provide a semiconductor memory device with improved degree of integration (Lee, ¶0004, ¶0045, ¶0058, ¶0062-¶0065).
Regarding claim 14, Shin in view of Lee discloses the semiconductor device of claim 12. Further, Shin discloses the semiconductor device, wherein a thickness in a vertical direction of each extension (170) (Shin, Figs. 3, 4C, 6, ¶0036, ¶0053, ¶0061-¶0062) of the first dummy vertical structures (DCH2a) is substantially same as a thickness in the vertical direction of the ground selection gate patterns (131).
Regarding claim 15, Shin in view of Lee discloses the semiconductor device of claim 12. Further, Shin discloses the semiconductor device, wherein the cell gate patterns (132-136) (Shin, Figs. 3, 4C, 6, ¶0036, ¶0053, ¶0061-¶0062) surround the vertical portions (140/150) of the first and second dummy vertical structures.
Regarding claim 16, Shin in view of Lee discloses the semiconductor device of claim 12. Further, Shin does not specifically disclose the semiconductor device, wherein the ground selection gate patterns surround each extension of the second dummy vertical structures.
However, Lee teaches forming the semiconductor memory device (Lee, Fig. 3, 4A, 5A-5D, 6B, ¶0045, ¶0058, ¶0062-¶0068, ¶0095-¶0096), wherein the ground selection gate patterns (50L) surround each extension (e.g., 26 in Fig. 4A and 47 in Fig. 6) of the dummy vertical structures (40d).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Shin/Lee by forming each dummy vertical structure including an insulating extension layer as taught by Lee to have the semiconductor device, wherein the ground selection gate patterns surround each extension of the second dummy vertical structures, in order to isolate data storage pattern, and to provide a semiconductor memory device with improved degree of integration (Lee, ¶0004, ¶0045, ¶0058, ¶0062-¶0065).
Regarding claim 17, Shin in view of Lee discloses the semiconductor device of claim 12. Further, Shin discloses the semiconductor device, wherein diameters of the vertical portions (e.g., channel portions 105/140/150) (Shin, Figs. 3,4C, 6, ¶0043, ¶0045-¶0047, ¶0061) of the first dummy vertical structures (DCH2a) are equal to diameters (e.g., the dummy structures DCH including DCH2a and DCH1 have the same structure as that of the channels CH) of the vertical portions of the second dummy vertical structures (DCH1).
Regarding claim 18, Shin in view of Lee discloses the semiconductor device of claim 12. Further, Shin discloses the semiconductor device, wherein the first and second dummy vertical structures (e.g., DCH2a and DCH1) are formed of an insulating material (e.g., the core including insulating layer 150) (Shin, Figs. 3, 4A, 4C, 6, ¶0043, ¶0053, ¶0061-¶0062).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0303413 to Shin in view of Lee (US 2020/0127126) as applied to claim 12, and further in view of Ha (US 2018/0122742).
Regarding claim 13, Shin in view of Lee discloses the semiconductor device of claim 12. Further, Shin does not specifically disclose the semiconductor device, wherein each of the cell gate patterns has a first thickness in a vertical direction, and each of the ground selection gate patterns has a second thickness in the vertical direction that is greater than the first thickness.
However, Ha teaches forming the semiconductor device (Ha, Fig. 3, ¶0026-¶0030) with enhanced reliability, wherein each of the cell gate patterns (120b) has a first thickness (T2) in a vertical direction, and each of the ground selection gate patterns (120a) has a second thickness (T1) in the vertical direction that is greater than the first thickness (T2), to have increased channel length and larger threshold voltage to provide memory string with increased current and improved current controllability (Ha, ¶0005, ¶0030).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Shin/Lee by forming the cell gate patterns and the ground selection gate patterns having specific thicknesses as taught by Ha to have the semiconductor device, wherein each of the cell gate patterns has a first thickness in a vertical direction, and each of the ground selection gate patterns has a second thickness in the vertical direction that is greater than the first thickness, in order to have increased channel length and larger threshold voltage to provide memory string with increased current and improved current controllability (Ha, ¶0005, ¶0030).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0303413 to Shin in view of Lee (US 2020/0127126) as applied to claim 12, and further in view of Choi et al. (US 2020/0212061, hereinafter Choi).
Regarding claim 19, Shin in view of Lee discloses the semiconductor device of claim 12. Further, Shin does not specifically disclose the semiconductor device, further comprising through contact plugs connected to pad portions of the cell gate patterns in the connection region, wherein each of the second dummy vertical structures is disposed around a respective through contact plug.
However, Choi teaches forming a semiconductor device (Choi, Fig. 1A, 2A, ¶0004-¶0006, ¶0061-¶0064, ¶0077-¶0081) with high reliability and high integration density, wherein through contact plugs (CPLG) are provided in the connection region (CNR) to be connected to pad portions (ELp) of the cell gate patterns (EL), and wherein each of the second dummy vertical structures (VS2) is disposed around a respective through contact plug (CPLG), to prevent electric short circuit between the cell contact plugs.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Shin/Lee by forming the cell contact plugs enclosed by a plurality of dummy vertical structures as taught by Choi to have the semiconductor device, further comprising through contact plugs connected to pad portions of the cell gate patterns in the connection region, wherein each of the second dummy vertical structures is disposed around a respective through contact plug, in order to prevent electric short circuit between the cell contact plugs and to provide a semiconductor device with high reliability and high integration density (Choi, ¶0004, ¶0063, ¶0077, ¶0081).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0303413 to Shin in view of Seo et al (US 2022/0208783, hereinafter Seo).
With respect to claim 20, Shin discloses an electronic system (e.g., memory cell array and control logic) (Shin, Figs. 1, 3, 4A-4D, 5-6, 11, ¶0020-¶0073) comprising:
a semiconductor device including a substrate (101) (Shin, Figs. 1, 3, 4A-4D, ¶0033-¶0035) including a cell array region (I) and a connection region (II), a plurality of ground selection gate patterns (e.g., gate electrode 131 used as a ground select line is divided into subgate electrodes 131a and 131b) (Shin, Figs. 1, 3, 4A-4D, 5, ¶0059) with each ground selection gate pattern spaced apart (e.g., by MS2 and GS) from each other and disposed at the same level from a top surface of the substrate (101), a plurality of cell gate patterns (e.g., a plurality of cell gate patterns 132-136 divided by isolation regions MS2) (Shin, Figs. 1, 3, 4A-4D, 5, ¶0036, ¶0056-¶0058) vertically stacked on the plurality of ground selection gate patterns (131a/131b), separation structures (e.g., isolation regions MS2 divided by the lower isolation region GS/GSa) (Shin, Figs. 3, 4A-4D, 5-6, ¶0037, ¶0050-¶0051, ¶0061) vertically extending into the cell gate patterns (132-136) and disposed between adjacent ground selection gate patterns (131a/131b) of the plurality of ground selection gate patterns, and spaced apart from each other in the connection region (II) in a first direction (e.g., X-direction), and dummy vertical structures (e.g., a plurality of dummy channels DCH2a arranged in the X-direction and extending into the lower isolation region GSa, as in Fig. 6) (Shin, Figs. 3, 4C, 6, ¶0046-¶0047, ¶0053, ¶0061-¶0062) between adjacent separation structures (e.g., MS2) and between the adjacent ground selection gate patterns (131a/131b); and
a controller (36) (Shin, Figs. 1, ¶0024-¶0025) electrically connected to the semiconductor device (20) and controlling the semiconductor device (20),
wherein each of the dummy vertical structures (e.g., the plurality of dummy channels DCH2a arranged in the X-direction and extending into the lower isolation region GSa, as in Fig. 6) (Shin, Figs. 3, 4C, 6, ¶0046-¶0047, ¶0053, ¶0061-¶0062) includes:
a vertical portion (e.g., channel portions 105/140/150) (Shin, Figs. 3,4C, 6, ¶0043, ¶0045, ¶0047, ¶0061) that vertically extends into the cell gate patterns; and
an extension (e.g., an insulation layer 170 of the isolation region GSa in Fig. 6) (Shin, Figs. 3,4C, 6, ¶0053, ¶0061-¶0062) that protrudes horizontally from the vertical portion at the same level as the ground selection gate patterns (131a/131b), and
wherein the extension (e.g., an insulation layer 170 of the GS region) (Shin, Figs. 3, 4C, 6, ¶0053, ¶0061-¶0062) of each of the dummy vertical structures (e.g., DCH2a arranged in the X-direction and extending into the lower isolation region GSa, as in Fig. 6) are connected to each other and are in contact with the separation structures (MS2) adjacent to each other in the first direction (e.g., the X-direction).
Further, Shin does not specifically disclose an input/output pad electrically connected to peripheral circuits; and a controller electrically connected to the semiconductor device through the input/output pad.
However, Shin teaches that the controller (36) (Shin, Fig. 1, ¶0025, ¶0026) includes input and output circuit to transfer data to the buffer circuit (34) connected to the memory cell array (20).
Further, Seo teaches forming an electronic system (1000) (Seo, Fig. 1, ¶0020-¶0032) comprising an input/output pad (1101) electrically connected to peripheral circuits (1130); and a controller (1220) electrically connected to the semiconductor device (1100) through the input/output pad (1101), to provide an electronic system comprising a semiconductor device three-dimensionally arranged to improve integration density and reliability (Seo, ¶0003-¶0004, ¶0020-¶0032).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the electronic system of Shin by providing a connection between the controller and the semiconductor device through the input/output pad as taught by Seo to have the electronic system comprising: an input/output pad electrically connected to peripheral circuits; and a controller electrically connected to the semiconductor device through the input/output pad, in order to provide an electronic system comprising a semiconductor device three-dimensionally arranged to improve integration density and reliability (Seo, ¶0003-¶0004, ¶0020-¶0032).
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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