DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/27/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is rejected under 35 U.S.C. 103 as being unpatentable over Nishimura (US Patent Application Publication 2022/0139794A1).
Regarding claim 1, Nishimura (US Patent Application Publication 2022/0139794A1) teaches a semiconductor device (diode module 200, Figure 1, paragraph 0028) having an active region (active region, Figure 1, paragraph 0028) and a termination region (termination region, Figure 1, paragraph 0028) surrounding a periphery of the active region, the semiconductor device comprising: in the termination region, a semiconductor substrate (semiconductor substrate 1, Figure 1, paragraphs 0028 – 0029) of a first conductivity type; a first semiconductor region (drift layer 12, Figure 1, paragraphs 0029-0030) of the first conductivity type, provided on a surface of the semiconductor substrate; an insulating film (passivation film 4, Figure 1, paragraphs 0031 + 0033 + 0038-0040) provided on a surface of the first semiconductor region; and a polyimide film (polyimide film 6, Figure 1, paragraphs 0032 + 0038 + 0040-0041) selectively provided on a surface of the insulating film, as claimed.
Nishimura (US Patent Application Publication 2022/0139794A1) is silent to teach the first semiconductor region having a thickness “d” and wherein the polyimide film is provided at least a distance of 0.66d from an outer periphery end of the semiconductor device. However, Figure 1 of Nishimura (US Patent Application Publication 2022/0139794A1) shows the drift layer having a thickness, such that where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation (MPEP 2144.05). Further, Figure 1 of Nishimura (US Patent Application Publication 2022/0139794A1) shows the polyimide film a distance from an outer periphery end of the semiconductor device (Figure 1, paragraph 0028 + 0032), such that where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation (MPEP 2144.05).
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Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have optimized the teachings of Nishimura (US Patent Application Publication 2022/0139794A1) thereby having the polyimide film disposed to not extend to the outer periphery of the semiconductor device.
Claim(s) 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Nishimura (US Patent Application Publication 2022/0139794A1) in view of Hoshi (US Patent Application Publication 2022/0344455A1).
Regarding claim 2, Nishimura (US Patent Application Publication 2022/0139794A1) teaches the semiconductor device according to claim 1, as claimed.
Nishimura (US Patent Application Publication 2022/0139794A1) is silent to teach wherein the semiconductor device has a side surface at the outer periphery end thereof that is inclined at θ degrees inward from vertical, and the polyimide film is provided at least a distance of 0.66d+dtanθ from the outer periphery end of the semiconductor device. However, Figure 1 of Nishimura (US Patent Application Publication 2022/0139794A1) shows the polyimide film a distance from an outer periphery end of the semiconductor device (Figure 1, paragraph 0028 + 0032), such that where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation (MPEP 2144.05).
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In an analogous art, Hoshi (US Patent Application Publication 2022/0344455A1) teaches a semiconductor device with a side surface at the outer periphery end that is inclined at θ degrees inward from vertical (Figure 2, paragraph 0118).
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Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the outer periphery of the semiconductor device of Nishimura (US Patent Application Publication 2022/0139794A1) to have the inward angle as taught by Hoshi (US Patent Application Publication 2022/0344455A1) thereby having the polyimide film disposed to not extend to the outer periphery of the semiconductor device.
Regarding claim 3, Nishimura (US Patent Application Publication 2022/0139794A1) teaches the semiconductor device according to claim 1, as claimed.
Nishimura (US Patent Application Publication 2022/0139794A1) is silent to teach wherein the semiconductor device has a side surface at the outer periphery end thereof that is inclined at θ degrees inward from vertical, the semiconductor substrate has a thickness “D”, and the polyimide film is provided at least a distance of 0.66d+Dtanθ from the outer periphery end of the semiconductor device. However, Figure 1 of Nishimura (US Patent Application Publication 2022/0139794A1) shows the semiconductor substrate having a thickness, such that where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation (MPEP 2144.05). Further, Figure 1 of Nishimura (US Patent Application Publication 2022/0139794A1) shows the polyimide film a distance from an outer periphery end of the semiconductor device (Figure 1, paragraph 0028 + 0032), such that where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation (MPEP 2144.05).
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In an analogous art, Hoshi (US Patent Application Publication 2022/0344455A1) teaches a semiconductor device with a side surface at the outer periphery end thereof that is inclined at θ degrees inward from vertical (Figure 2, paragraph 0118).
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Therefore, it would have been obvious for some one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the outer periphery of the semiconductor substrate of Nishimura (US Patent Application Publication 2022/0139794A1) to have an inward angle as taught by Hoshi (US Patent Application Publication 2022/0344455A1) thereby having the polyimide film disposed to not extend to the outer periphery of the semiconductor device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREEM M MOHAMED-ALY whose telephone number is (571)270-0312. The examiner can normally be reached 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KAREEM M MOHAMED-ALY/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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