DETAILED ACTION
General Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
5. Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form
(http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
6. Status of claim(s) to be treated in this office action:
a. Independent: 1, 12 and 20.
b. Pending: 1-20.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liikanen US Patent 10446241 (hereinafter Liikanen).
Regarding independent claim 1, Liikanen teaches a memory system (title), comprising:
a memory device (102 in figure 1, [9], “…a memory component comprising a memory region having a plurality of memory cells configured to read out data states in response to application of a current read level signal…”) comprising a plurality of memory cells, wherein each of the plurality of memory cells is configured to be in one of a plurality of data states; and
a memory controller (106 in figure 1) coupled with the memory device and configured to:
perform a read operation using a test read voltage corresponding to a selected data state among the plurality of data states (230 in figure 2, [21], “…controller 106 can …send a read request …that include read level signals (e.g., read level voltages) … and read out data states stored on the memory cells 122 ...”);
acquire a count of memory cells each having a threshold voltage that satisfies a preset condition, wherein the preset condition comprises: the threshold voltage being less than or equal to the test read voltage, or the threshold voltage being greater than or equal to the test read voltage (Liikanen teaches counting memory cells that output a specified data state in response to each applied read voltage test signal, [38], “…calibration circuitry 110 can determine a number of memory cells within the memory region (e.g., a count) that output a specified data state (e.g., a current above a threshold value and/or a current below a threshold value). In the embodiment illustrated in FIG. 4D, the calibration circuitry 110 determines a count as each of the test signals V.sub.L2, V.sub.L1, V.sub.A, V.sub.U1, V.sub.U2 are applied to the memory region…”);
determine a difference between the count and an expected count (Liikanen teaches calculating count differences between counts associated with different read level test signals and identifying a minimum count difference, [39], “…calibration circuitry 110 can calculate count differences between the counts corresponding to adjacent test signals…”, [41], “…calibration circuitry 110 may determine a read level offset value based on the minimum count difference m…”, “expect count” has been interpreted as “a target behavior, a reference condition, a desired outcome”, Liikanen teaches evaluating multiple counts produced by multiple test read voltages, and comparing those counts to determine which behavior is closest to ideal, thus, that “ideal” behavior is the expected count, Liikanen establishes an expected behavior as “optimal read level occurs where count differences are minimized”, “expected count” treated as “reference count representing desired or target behavior”); and
acquire at least one read retry voltage according to the difference, a mapping relationship, and a read retry table, wherein the mapping relationship comprises a correspondence between an expected voltage offset value and the difference (Liikanen teaches determining a read level offset value based on the count differences, including extrapolating a voltage value between test signals and using it to adjust the read level signal, [43],m “..the calibration circuitry 110 can extrapolate a value between adjacent relative differences…the calibration circuitry 110 may determine a read level offset value corresponding to a distance between the base read level signal (e.g., the first base read level test voltage V.sub.A) and the extrapolated value 483…”, Liikanen further teaches storing and using the offset value to update the read level signal for subsequent read operations, [54], “…in subsequent iterations of read level calibration of the selected memory region (either walking calibrations or non-walking calibrations), the calibration value can be updated by adding the newly-obtained average total read level offset value(s) from the routine 580 to the stored calibration value…”)
Regarding claim 2, Liikanen teaches the memory system of claim 1, wherein the count comprises a first count of memory cells each having a threshold voltage less than or equal to the test read voltage among the plurality of memory cells (Liikanen teaches applying read-level test signals and counting memory cells that respond to the applied read level, [38], “…calibration circuitry 110 can determine a number of memory cells within the memory region (e.g., a count) that output a specified data state…”), the expected count comprises a first expected count (“expected count” has been understood as desired outcome occurs at the default read voltage, desired behavior is understood as nominal or based line operating behavior, Liikanen teaches the use of base read level test signal that represents nominal or baseline read behavior, [29], “…first read level offset value is utilized to determine an improved read level test signal that serves as a base read level test signal for a next calibration step. Referring to plot 442 of FIG. 4B, the first read level offset value in this example is equal to the difference of a voltage value of test signal V.sub.U2 and a base read level test signal (which in this example has the same voltage of the current read level signal V.sub.A)…”), which is a preset count of memory cells each having a threshold voltage less than or equal to a default read voltage among the plurality of memory cells, the mapping relationship comprises a first mapping relationship, which is acquired based on the first expected count, and the memory controller is further configured to: acquire a first expected voltage offset value according to a first difference between the first count and the first expected count (Liikanen teaches determining a read-level offset value based on relative count differences and the voltages spacing between applied read-level test signals), the first mapping relationship, and a voltage difference between the test read voltage and the default read voltage (Liikanen teaches determining a read-level offset value based on relative count differences and the voltages spacing between applied read-level test signals); and
acquire at least one first voltage offset value from the read retry table according to the first expected voltage offset value (Liikanen teaches storing calibration results and using them to update the current read-level signal during subsequent read operations), [54], “…routine 570 can store the updated calibration value and/or the updated current read level signal in, for example, a table…”)
Regarding claim 3, Liikanen teaches the memory system of claim 2, wherein the at least one first voltage offset value is stored in the read retry table in order of magnitude (Liikanen teaches generating multiple read-level offset values positioned above and below a base (default) read -level signal, [28], “…the calibration circuitry 110 applies five test signals to the memory region containing the depicted memory cell. More specifically, the calibration circuitry 110 applies the current read level signal V.sub.A (i.e., a first base read level test signal V.sub.A), two upper test signals V.sub.U1, V.sub.U2 offset (e.g., at 20 mV intervals) above the base read level test signal V.sub.A, and two lower test signals V.sub.IA, V.sub.L2 offset (e.g., at 20 mV intervals) below the base read level test signal V.sub.A…”, although Liikanen does not explicitly teach state that the offset values are “stored in order of magnitude”, it would have been obvious to store such offset values ordered by magnitude, because the offset inherently defined relative to a based voltages and ordered storage enables efficient selection during read-retry operations).
Regarding claim 4, Liikanen teaches the memory system of claim 3, wherein the at least one first voltage offset value comprises one or more first voltage offset values equal to the first expected voltage offset value (Liikanen teaches determining a read-level offset value based on calibration results, [41], “…the calibration circuitry 110 may determine the read level offset value…”, Liikanen further teaches using the determined offset value directly to update the current read-level signal, [45], “…controller 106 and/or the host 108 may add the total read level offset value to the amount the current read level test signal is set at…”. It would have been obvious to include, in the stored offset values, an offset equal to the expected (determined) offset value, because Liikanen already teaches directly applying that determined offset without modification).
Regarding claim 5, Liikanen teaches the memory system of claim 3, wherein the memory controller is further configured to: generate an offset value range according to the first expected voltage offset value, wherein the first expected voltage offset value is within the offset value range; and acquire the at least one first voltage offset value located within the offset value range from the read retry table (Liikanen teaches applying multiple read-level test signals around a base read-level signal, spanning both higher and lower voltages, Liikanen further teaches evaluating multiple neighboring read levels during calibration to determine an optical offset, defining an offset value range centered on an expected offset value, and selecting offsets within that range, would have been obvious, because Liikanen already discloses using a plurality of offsets around a base value, and limiting selection to a range around an expected value is a routine optimization to reduce calibration time and improve convergence).
Regarding claim 6, Liikanen teaches the memory system of claim 5, wherein a maximum value of the offset value range is the first expected voltage offset value plus a first step length, and a minimum value of the offset value range is the first expected voltage offset value minus a second step length (Liikanen teaches applying multiple read-level test signals around a base read-level signal, spanning both higher and lower voltages, suing fixed voltage increments , [28], “…the calibration circuitry 110 applies five test signals to the memory region containing the depicted memory cell. More specifically, the calibration circuitry 110 applies the current read level signal V.sub.A (i.e., a first base read level test signal V.sub.A), two upper test signals V.sub.U1, V.sub.U2 offset (e.g., at 20 mV intervals) above the base read level test signal V.sub.A, and two lower test signals V.sub.IA, V.sub.L2 offset (e.g., at 20 mV intervals) below the base read level test signal V.sub.A…”, although Liikanen does not explicitly label the boundary as a “maximum” or “minimum” of a range, it would have been obvious to define the offset search window as +/_step lengths around an expected offset value, because Liikanen already teaches symmetric stepping about a vase level using known increments).
Regarding claim 7, Liikanen teaches the memory system of claim 5, wherein the memory controller is further configured to: acquire a plurality of adjacent first voltage offset values from the read retry table (Liikanen teaches performing multiple calibration steps using neighboring read-level test signals during walking read-level calibration, retrieving adjacent offset values from a stored set (e.g., table) would have been obvious, because Liikanen’s method inherently relied on adjacent voltage steps to converge on an optimal read level).
Regarding claim 8, Liikanen teaches the memory system of claim 3, wherein the memory cells are multi-bit memory cells, and the plurality of data states are distinguished from each other by multi-level read voltages, and the read retry table is configured to store second voltage offset values corresponding to at least one level of read voltage, wherein the second voltage offset values corresponding to a highest level of read voltage are stored in order of magnitude, and the at least one first voltage offset value is included in the second voltage offset values corresponding to the highest level of read voltage (Liikanen teaches memory cells having more than 2 threshold voltages and the use of multiple read-level signals for such multi-bit memory cells, it would have been obvious to store offset values per read level and to organize those offsets by magnitude, because Liikanen already teaches distinct read levels and offset values associated with those values, and magnitude ordering is a routine data-organization technique facilitating efficient selection).
Regarding claim 9, Liikanen teaches the memory system of claim 8, wherein the multi-level read voltages are divided into a plurality of groups, the read retry table comprises a plurality of read retry sub-tables, wherein one of the read retry sub-tables is configured to store the second voltage offset values corresponding to at least one level of read voltage in one of the groups, the second voltage offset values corresponding to the highest level of read voltage are stored in the read retry sub-table in order of magnitude, and the at least one first voltage offset value is included in the second voltage offset values corresponding to the highest level of read voltage in the read retry sub-table (Liikanen teaches grouping calibration operations by read-level iteration and calibration state, and maintaining calibration values associated with those stages [27], [52], organizing stored offset values into sub-tables corresponding to groups of read levels would have been obvious, as it is predictable organizational choice that follow directly from Liikanen’s grouped calibration processed).
Regarding claim 10, Liikanen teaches the memory system of claim 2, wherein the first count of memory cells each having a threshold voltage less than the test read voltage among the plurality of memory cells is greater than a second count of memory cells each having a threshold voltage greater than the test read voltage among the plurality of memory cells (Liikanen teaches comparing counts obtained at different read-level test signals to evaluate read-level accuracy, determining whether one count is greater than another is inherent in Liikanen’s disclosed count-comparison process and would have been obvious to implement as a comparison condition).
Regarding claim 11, Liikanen teaches the memory system of claim 2, wherein the memory controller is configured to: sum the default read voltage and the at least one first voltage offset value to obtain the corresponding read retry voltage (Liikanen teaches an updated read-level signal by adding offset to the current/base read-level signal).
Regarding independent claim 12, Liikanen teaches a control method of a memory system, comprising:
performing a read operation on a plurality of memory cells using a test read voltage corresponding to a selected data state among a plurality of data states, wherein each of the plurality of memory cells is configured to be in one of the plurality of data states (230 in figure 2, [21], “…controller 106 can …send a read request …that include read level signals (e.g., read level voltages) … and read out data states stored on the memory cells 122 ...”);
acquiring a count of memory cells each having a threshold voltage that satisfies a preset condition, wherein the preset condition comprises: the threshold voltage being less than or equal to the test read voltage, or the threshold voltage being greater than or equal to the test read voltage (Liikanen teaches counting memory cells that output a specified data state in response to each applied read voltage test signal, [38], “…calibration circuitry 110 can determine a number of memory cells within the memory region (e.g., a count) that output a specified data state (e.g., a current above a threshold value and/or a current below a threshold value). In the embodiment illustrated in FIG. 4D, the calibration circuitry 110 determines a count as each of the test signals V.sub.L2, V.sub.L1, V.sub.A, V.sub.U1, V.sub.U2 are applied to the memory region…”);
determining a difference between the count and an expected count (Liikanen teaches calculating count differences between counts associated with different read level test signals and identifying a minimum count difference, [39], “…calibration circuitry 110 can calculate count differences between the counts corresponding to adjacent test signals…”, [41], “…calibration circuitry 110 may determine a read level offset value based on the minimum count difference m…”, “expect count” has been interpreted as “a target behavior, a reference condition, a desired outcome”, Liikanen teaches evaluating multiple counts produced by multiple test read voltages, and comparing those counts to determine which behavior is closest to ideal, thus, that “ideal” behavior is the expected count, Liikanen establishes an expected behavior as “optimal read level occurs where count differences are minimized”, “expected count” treated as “reference count representing desired or target behavior”); and
acquiring at least one read retry voltage according to the difference, a mapping relationship, and a read retry table, wherein the mapping relationship comprises a correspondence between an expected voltage offset value and the difference (Liikanen teaches determining a read level offset value based on the count differences, including extrapolating a voltage value between test signals and using it to adjust the read level signal, [43],m “..the calibration circuitry 110 can extrapolate a value between adjacent relative differences…the calibration circuitry 110 may determine a read level offset value corresponding to a distance between the base read level signal (e.g., the first base read level test voltage V.sub.A) and the extrapolated value 483…”, Liikanen further teaches storing and using the offset value to update the read level signal for subsequent read operations, [54], “…in subsequent iterations of read level calibration of the selected memory region (either walking calibrations or non-walking calibrations), the calibration value can be updated by adding the newly-obtained average total read level offset value(s) from the routine 580 to the stored calibration value…”)
Regarding claim 13, Liikanen teaches the control method of claim 12, wherein the count comprises a first count of memory cells each having a threshold voltage less than or equal to the test read voltage among the plurality of memory cells (Liikanen teaches applying read-level test signals and counting memory cells that respond to the applied read level, [38], “…calibration circuitry 110 can determine a number of memory cells within the memory region (e.g., a count) that output a specified data state…”), the expected count comprises a first expected count (“expected count” has been understood as desired outcome occurs at the default read voltage, desired behavior is understood as nominal or based line operating behavior, Liikanen teaches the use of base read level test signal that represents nominal or baseline read behavior, [29], “…first read level offset value is utilized to determine an improved read level test signal that serves as a base read level test signal for a next calibration step. Referring to plot 442 of FIG. 4B, the first read level offset value in this example is equal to the difference of a voltage value of test signal V.sub.U2 and a base read level test signal (which in this example has the same voltage of the current read level signal V.sub.A)…”), which is a preset count of memory cells each having a threshold voltage less than or equal to a default read voltage among the plurality of memory cells, the mapping relationship comprises a first mapping relationship, which is acquired based on the first expected count (Liikanen teaches determining a read-level offset value based on relative count differences and the voltages spacing between applied read-level test signals), and the control method further comprises: acquiring a first expected voltage offset value according to a first difference between the first count and the first expected count, the first mapping relationship, and a voltage difference between the test read voltage and the default read voltage (Liikanen teaches storing calibration results and using them to update the current read-level signal during subsequent read operations), [54], “…routine 570 can store the updated calibration value and/or the updated current read level signal in, for example, a table…”); and acquiring at least one first voltage offset value from the read retry table according to the first expected voltage offset value.
Regarding claim 14, Liikanen teaches the control method of claim 13, wherein the at least one first voltage offset value is stored in the read retry table in order of magnitude (Liikanen teaches generating and storing multiple offset values around a base read level, storing offset values ordered by magnitude in a read-retry table is a routine data organization choice that would have been obvious to improve efferent retry selection).
Regarding claim 15, Liikanen teaches the control method of claim 14, wherein the at least one first voltage offset value comprises one or more first voltage offset values equal to the first expected voltage offset value (Liikanen teaches determining a read-level offset value based on calibration results, [41], “…the calibration circuitry 110 may determine the read level offset value…”, Liikanen further teaches using the determined offset value directly to update the current read-level signal, [45], “…controller 106 and/or the host 108 may add the total read level offset value to the amount the current read level test signal is set at…”. It would have been obvious to include, in the stored offset values, an offset equal to the expected (determined) offset value, because Liikanen already teaches directly applying that determined offset without modification).
Regarding claim 16, Liikanen teaches the control method of claim 14, further comprising: generating an offset value range according to the first expected voltage offset value, wherein the first expected voltage offset value is within the offset value range; and acquiring the at least one first voltage offset value located within the offset value range from the read retry table (Liikanen teaches applying multiple read-level test signals around a base read-level signal, spanning both higher and lower voltages, Liikanen further teaches evaluating multiple neighboring read levels during calibration to determine an optical offset, defining an offset value range centered on an expected offset value, and selecting offsets within that range, would have been obvious, because Liikanen already discloses using a plurality of offsets around a base value, and limiting selection to a range around an expected value is a routine optimization to reduce calibration time and improve convergence).
Regarding claim 17, Liikanen teaches the control method of claim 16, wherein a maximum value of the offset value range is the first expected voltage offset value plus a first step length, and a minimum value of the offset value range is the first expected voltage offset value minus a second step length (Liikanen teaches symmetric stepping around the base read level using defined voltage offsets, defining the offset range bounds as +/_ step lengths is an obvious formalization of this stepping scheme).
Regarding claim 18, Liikanen teaches the control method of claim 16, further comprising: acquiring a plurality of adjacent first voltage offset values from the read retry table (Liikanen teaches performing multiple calibration steps using neighboring read-level test signals during walking read-level calibration, retrieving adjacent offset values from a stored set (e.g., table) would have been obvious, because Liikanen’s method inherently relied on adjacent voltage steps to converge on an optimal read level).
Regarding claim 19, Liikanen teaches the control method of claim 14, wherein the memory cells are multi-bit memory cells, and the plurality of data states are distinguished from each other by multi-level read voltages, and the read retry table is configured to store second voltage offset values corresponding to at least one level of read voltage, wherein the second voltage offset values corresponding to a highest level of read voltage are stored in order of magnitude, and the at least one first voltage offset value is included in the second voltage offset values corresponding to the highest level of read voltage (Liikanen teaches memory cells having more than 2 threshold voltages and the use of multiple read-level signals for such multi-bit memory cells, it would have been obvious to store offset values per read level and to organize those offsets by magnitude, because Liikanen already teaches distinct read levels and offset values associated with those values, and magnitude ordering is a routine data-organization technique facilitating efficient selection).
Regarding independent claim 20, Liikanen teaches a readable storage medium, storing a computer program which, when executed, implements a control method of a memory system (Liikanen teaches calibration logic implemented by computer firmware or stored instructions [52]-[53]), wherein the control method comprises:
performing a read operation on a plurality of memory cells using a test read voltage corresponding to a selected data state among a plurality of data states, wherein each of the plurality of memory cells is configured to be in one of the plurality of data states (230 in figure 2, [21], “…controller 106 can …send a read request …that include read level signals (e.g., read level voltages) … and read out data states stored on the memory cells 122 ...”);
acquiring a count of memory cells each having a threshold voltage that satisfies a preset condition, wherein the preset condition comprises: the threshold voltage being less than or equal to the test read voltage, or the threshold voltage being greater than or equal to the test read voltage (Liikanen teaches counting memory cells that output a specified data state in response to each applied read voltage test signal, [38], “…calibration circuitry 110 can determine a number of memory cells within the memory region (e.g., a count) that output a specified data state (e.g., a current above a threshold value and/or a current below a threshold value). In the embodiment illustrated in FIG. 4D, the calibration circuitry 110 determines a count as each of the test signals V.sub.L2, V.sub.L1, V.sub.A, V.sub.U1, V.sub.U2 are applied to the memory region…”);
determining a difference between the count and an expected count (Liikanen teaches calculating count differences between counts associated with different read level test signals and identifying a minimum count difference, [39], “…calibration circuitry 110 can calculate count differences between the counts corresponding to adjacent test signals…”, [41], “…calibration circuitry 110 may determine a read level offset value based on the minimum count difference m…”, “expect count” has been interpreted as “a target behavior, a reference condition, a desired outcome”, Liikanen teaches evaluating multiple counts produced by multiple test read voltages, and comparing those counts to determine which behavior is closest to ideal, thus, that “ideal” behavior is the expected count, Liikanen establishes an expected behavior as “optimal read level occurs where count differences are minimized”, “expected count” treated as “reference count representing desired or target behavior”); and
acquiring at least one read retry voltage according to the difference, a mapping relationship, and a read retry table, wherein the mapping relationship comprises a correspondence between an expected voltage offset value and the difference (Liikanen teaches determining a read level offset value based on the count differences, including extrapolating a voltage value between test signals and using it to adjust the read level signal, [43],m “..the calibration circuitry 110 can extrapolate a value between adjacent relative differences…the calibration circuitry 110 may determine a read level offset value corresponding to a distance between the base read level signal (e.g., the first base read level test voltage V.sub.A) and the extrapolated value 483…”, Liikanen further teaches storing and using the offset value to update the read level signal for subsequent read operations, [54], “…in subsequent iterations of read level calibration of the selected memory region (either walking calibrations or non-walking calibrations), the calibration value can be updated by adding the newly-obtained average total read level offset value(s) from the routine 580 to the stored calibration value…”)
Conclusion
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824