DETAILED ACTION
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Raghavan et al. (US 20150162448 A1, hereinafter Rag’448).
Regarding independent claim 1, Rag’448 teaches, “A semiconductor device (fig. 1-6; ¶ [0001] - ¶ [0039]) comprising:
a first semiconductor chip including:
a semiconductor substrate including:
a plurality of circuit elements (fig. 1; ¶ [0020]); and
a wiring structure (BEOL) which is disposed on the semiconductor substrate, the wiring structure including:
a plurality of wiring layers (M1-M4); and
power gating elements (100) disposed in the plurality of wiring layers (M1-M4),
the power gating elements (100) being transistors respectively including:
channel portions (13) each including a two-dimensional semiconductor material (graphene, ¶ [0037]);
gate electrodes (10);
source electrodes (11); and
drain electrodes (12)”.
Regarding claim 9, Rag’448 further teaches, “The semiconductor device of claim 1, wherein: each of the plurality of wiring layers (M1-M4, fig. 1) comprises: a lower inter-insulating layer (5); an upper inter-insulating layer (4) on the lower inter-insulating layer (5); and metal lines (2) and connection vias (3) buried in the lower inter-insulating layer (5) and the upper inter-insulating layer (4)”.
Regarding claim 10, Rag’448 further teaches, “The semiconductor device of claim 9, wherein: the gate electrodes (10, fig. 1), the source electrodes (11), and the drain electrodes (12) of the power gating elements (100) include a same material as a material of at least some of the metal lines and the connection vias (electrodes 10, 11 and 12 are formed as part of metal lines and vias in wiring layers M3-M4, ¶ [0024]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 9-10 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over VAN DAL et al. (US 20200135929 A1, hereinafter Van’929) in view of Choi et al. (US 20200194596 A1, hereinafter Choi’596).
Regarding independent claim 1, Van’929 teaches, “A semiconductor device (fig. 1-23; ¶ [0001] - ¶ [0084]) comprising:
a first semiconductor chip including:
a semiconductor substrate (‘semiconductor substrate’, fig. 2; ¶ [0031]) including:
a plurality of circuit elements (‘MOS transistors’, ¶ [0031]); and
a wiring structure which is disposed on the semiconductor substrate, the wiring structure including:
a plurality of wiring layers (BEOL); and
power gating elements (TFTs, ‘power switch circuit (header and/or footer switch)’, ¶ [0031] - ¶ [0032]) disposed in the plurality of wiring layers, the power gating elements being transistors respectively including: channel portions ((each including a two-dimensional semiconductor material)); gate electrodes; source electrodes; and drain electrodes (TFT elements)”.
But Van’929 is silent upon the provision of wherein the channel portions each including a two-dimensional semiconductor material.
However, Choi’596 teaches a similar thin-film transistor (fig. 1), wherein the channel portions (110) each including a two-dimensional semiconductor material (TMDC).
Van’929 and Choi’596 are analogous art because they both are directed to thin-film transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Van’929 with the features of Choi’596 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Van’929 and Choi’596 to form the channel of the TFT using TMDC according to the teachings of Choi’596 ‘due to high mobility, atomic-layer-scale small thickness and high flexibility, transparency, etc. resulting from the thickness’. See Choi’596, ¶ [0002].
Note: Secondary art Choi’596 can be replaced by MAXEY; Kirby et al. (US 20220149192 A1, fig. 3A; ¶ [0041]) etc.
Regarding claim 2, Van’929 modified with Choi’596 further teaches, “The semiconductor device of claim 1, wherein: the power gating elements include a first power gating element and a second power gating element, and the first power gating element is a P-type transistor, and the second power gating element is an N-type transistor (Van’929, ¶ [0030])”.
Regarding claim 3, Van’929 modified with Choi’596 further teaches, “The semiconductor device of claim 2, wherein: a channel portion of the first power gating element among the channel portions includes at least one of SnS, SnSe2, GaSe, WS2, WSe₂, MoTe₂, WTe2, HfSe₂, ReS₂, ZrSe₂, PtSe₂, FeSe2, NiTe₂, GaTe₂, Germanium, Selenium, Tellurene, Phosphorene, Arsenene, Silicene, Stanene, and Borophene, and a channel portion of the second power gating element among the channel portions includes at least one of MoS2, TaS2, NbSe₂, MoSe₂, MoS2-xSex, TiS2, TaSe2, ZrS₂, HfS₂, ReSe2, PtS₂, PdSe2, PdTe2, VS₂, VSe₂, FeTe2, and Antimonene (Transition metal dichalcogenides, Choi’596).
Regarding claim 4, Van’929 modified with Choi’596 further teaches, “The semiconductor device of claim 2, wherein: a channel portion of the first power gating element among the channel portions includes at least one of MoS2, MoSe₂, MoTe₂, WS2, WSe₂, WTe₂, ZrS₂, ZrSe₂, HfS2, HfSe₂, NbSe₂, ReSe2, PtS₂, PtSe₂, PdSe₂, PdTe2, VS2, VSe₂, FeSe2, FeTe2, MoS(x)Se(1-x) (wherein 0<x<1), WS(x)Se(1-x) (wherein 0<x<1), Graphene, GaSe, GaTe₂, SnSe, Bi2Se3, Bi₂O₂Se, Silicene, Stanene, Tellurene, Borophene, and Antimonene, and has P-type semiconductor characteristics, and a channel portion of the second power gating element among the channel portions includes at least one of MoS2, MoSe₂, MoTe₂, WS2, WSe2, WTe₂, ZrS2, ZrSe₂, HfS2, HfSe₂, NbSe₂, ReSe2, PtS₂, PtSe₂, PdSe₂, PdTe₂, VS2, VSe₂, FeSe2, FeTe₂, MoS(x)Se(1-x) (wherein 0<x<1), WS(x)Se(1-x) (wherein 0<x<1), Graphene, GaSe, GaTe₂, SnSe, Bi2Se3, Bi₂O₂Se, Silicene, Stanene, Tellurene, Borophene, and Antimonene, and has N-type semiconductor characteristics (Transition metal dichalcogenides, Choi’596)”.
Regarding claim 5, Van’929 modified with Choi’596 further teaches, “The semiconductor device of claim 2, wherein: the first power gating element is a header, and the second power gating element is a footer (Van’929, ¶ [0030])”.
Regarding claim 9, Van’929 modified with Choi’596 further teaches, “The semiconductor device of claim 1, wherein: each of the plurality of wiring layers (M1-M9, fig. 2) comprises: a lower inter-insulating layer; an upper inter-insulating layer on the lower inter-insulating layer; and metal lines and connection vias buried in the lower inter-insulating layer and the upper inter-insulating layer”.
Regarding claim 10, Van’929 modified with Choi’596 further teaches, “The semiconductor device of claim 9, wherein: the gate electrodes, the source electrodes, and the drain electrodes of the power gating elements include a same material as a material of at least some of the metal lines and the connection vias (Van’929, ¶ [0039], ¶ [0066], ¶ [0042], ¶ [0071] Choi’596, ¶ [0033, 0038])”.
Regarding claim 14, Van’929 modified with Choi’596 further teaches, “The semiconductor device of claim 2, wherein: in the channel portions, at least one (Choi’596, ¶ [0054]) and no more than three layers of the two-dimensional semiconductor material are stacked”.
Claims 6-8 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Van’929 modified with Choi’596 as applied to claim 1 as above, and further in view of O'Brien et al. (US 20230411390 A1, hereinafter O'Brien’390).
Regarding claim 6, Van’929 modified with Choi’596 teaches all the limitations described in claim 1.
Van’929 further teaches, wherein the power gating elements include a first power gating element and a second power gating element (fig. 1-2, Van’929).
But Van’929 modified with Choi’596 is silent upon the provision of wherein a channel portion of the first power gating element among the channel portions includes an oxide semiconductor, and a channel portion of the second power gating element among the channel portions includes the two-dimensional semiconductor material.
However, O'Brien’390 teaches a similar device (fig. 1A-1B and 2), wherein a channel portion of the first power gating element (¶ [0031]: NMOS 242/252 implemented as NMOS 100
of fig.1A) among the channel portions includes an oxide semiconductor (IGZO, ¶ [0011]), and a channel portion of the second power gating element (¶ [0031]: PMOS 244/254
implemented as PMOS 120 of fig.1B) among the channel portions includes the two-dimensional semiconductor material (WSe2, ¶ [0013] - ¶ [0014]).
Van’929 modified with Choi’596 and O'Brien’390 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Van’929 modified with Choi’596 with the features of O'Brien’390 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Van’929 modified with Choi’596 and O'Brien’390 to include oxide semiconductor and two-dimensional semiconductor material for channel according to the teachings of O'Brien’390 which enables the use of CMOS logic circuits in the back-end of an integrated circuit device. See O'Brien’390, ¶ [0001].
Regarding claim 7, Van’929 modified with Choi’596 and O'Brien’390 further teaches, “The semiconductor device of claim 6, wherein: the channel portion of the second power gating element includes at least one of MoS2, MoSe₂, MoTe₂, WS2, WSe₂, WTe₂, ZrS₂, ZrSe₂, HfS2, HfSe₂, NbSe₂, ReSe₂, PtS₂, PtSe₂, PdSe₂, PdTe₂, VS₂, VSe₂, FeSe2, FeTe2, MoS(x)Se(1-x) (wherein 0<x<1), WS(x)Se(1-x) (wherein 0<x<1), Graphene, GaSe, GaTe₂, SnSe, Bi2Se3, Bi₂O₂Se, Silicene, Stanene, Tellurene, Borophene, and Antimonene (Transition metal dichalcogenides, Choi’596).
Regarding claim 8, Van’929 modified with Choi’596 and O'Brien’390 further teaches, “The semiconductor device of claim 7, wherein: the channel portion of the first power gating element includes at least one of ZnO, In2O3, TiO2, Ga2O₃, VOx, indium zinc oxide (InZnO), indium gallium zinc oxide, indium zinc aluminum oxide, SnO, Cu2O, and NiO (Van’929, ¶ [0033]).
Regarding claim 15, Van’929 modified with Choi’596 and O'Brien’390 further teaches, “The semiconductor device of claim 1, wherein: the power gating elements include a plurality of N-type transistors and a plurality of P-type transistors, and the plurality of N-type transistors and the plurality of P-type transistors constitute an efficient charge recovery logic circuit (fig. 2, Van’929)”.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Rag’448 as applied to claim 10 as above and further in view of Jain et al. (US 20210143127 A1, hereinafter Jain’127).
Regarding claim 11, Rag’448 teaches all the limitations described in claim 10.
But Rag’448 is silent upon the provision of wherein the semiconductor device of claim 10, further comprising:
a circuit board which includes wiring lines and a wiring pad,
wherein the first semiconductor chip includes a plug which passes through at least a portion of the semiconductor substrate and the wiring structure, and a plug pad which is disposed on a lower surface of the semiconductor substrate and is connected to the plug, and
the first semiconductor chip is disposed on the circuit board, and further includes a bump which connects the wiring pad and the plug pad.
However, Jain’127 teaches a similar device comprising: a circuit board (105, fig. 1) which includes wiring lines and a wiring pad, wherein the first semiconductor chip includes a plug (445, 435, fig. 4B) which passes through at least a portion of the semiconductor substrate (450) and the wiring structure, and a plug pad (whereby 445 is also implicitly provided with a "plug pad" since it is connected to bumps as shown in fig.1; ¶ [0049]) which is disposed on a lower surface of the semiconductor substrate and is connected to the plug, and the first semiconductor chip is disposed on the circuit board, and further includes a bump which connects the wiring pad and the plug pad (fig. 4B).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Rag’448 and Jain’127 to include circuit board and multiple chips according to the teachings of Jain’127 as these are essential componenets in a typical electrical circuit.
Regarding claim 12, Rag’448 modified with Jain’127 further teaches, “The semiconductor device of claim 11, further comprising: a second semiconductor chip bonded to an upper surface of the first semiconductor chip, wherein the second semiconductor chip receives power through the plug (fig. 4B, Jain’127)”.
Regarding claim 13, “The semiconductor device of claim 12, wherein: the plug passes through an entirety of the semiconductor substrate and an entirety of the wiring structure, and the plug is connected to the second semiconductor chip through a connection pad so as to apply the power to the second semiconductor chip”, Jain’127 teaches that the chip of fig.4B is configured to be "the base die in a die stack" (¶ [0049]) such that power (current 430 in fig.4B) is provided to the upper levels of the stack through plug 445-435.
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Van’929 in view of O'Brien et al. (US 20230420364 A1, hereinafter O'Brien’364) and Jain’127.
Regarding independent claim 16, Van’929 teaches, “A semiconductor device (fig. 1-23; ¶ [0001] - ¶ [0084]) comprising:
((a circuit board which includes circuit wiring;))
a first semiconductor chip which is disposed ((on the circuit board)), the first semiconductor chip including:
a semiconductor substrate (‘semiconductor substrate’, fig. 2; ¶ [0031]) including:
a plurality of circuit elements (‘MOS transistors’, ¶ [0031]); and
a wiring structure which is disposed on the semiconductor substrate, the wiring structure including:
a plurality of wiring layers (BEOL); and
a plurality of power gating elements (TFTs, ‘power switch circuit (header and/or footer switch)’, ¶ [0031] - ¶ [0032]) disposed in the plurality of wiring layers,
the plurality of power gating elements including N-type transistors and P-type transistors respectively (¶ [0030]) including:
((channel portions each including a two-dimensional semiconductor material; and
a second semiconductor chip which is disposed on the first semiconductor chip)).
But Van’929 is silent upon the provision of wherein the semiconductor device comprising:
a circuit board which includes circuit wiring;
the first semiconductor chip which is disposed on the circuit board,
….
channel portions each including a two-dimensional semiconductor material;
However, O'Brien’364 teaches a similar device (fig. 2) comprising:
a circuit board (202) which includes circuit wiring;
the first semiconductor chip which is disposed on the circuit board (202),
….
channel portions each including a two-dimensional semiconductor material (TMD, ¶ [0048]);
Van’929 and O'Brien’364 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Van’929 with the features of O'Brien’364 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Van’929 and O'Brien’364 to form the channel using TMD according to the teachings of O'Brien’364 to exploit the advantages of TMD materials, e.g., high mobility, atomic-layer-scale small thickness and high flexibility, transparency, etc.
But Van’929 modified with O'Brien’364 is silent upon the provision of wherein the semiconductor device comprising: a second semiconductor chip which is disposed on the first semiconductor chip.
However, Jain’127 teaches a similar device (fig. 1) comprising: a second semiconductor chip which is disposed on the first semiconductor chip (dies 121, 131, 141 on board 105).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Van’929, O'Brien’364 and Jain’127 to form chip stack on board according to the teachings of Jain’127 as stacking save space and reduce the size of the chip thus saving cost.
Regarding claim 17, Van’929 modified with O'Brien’364 and Jain’127 further teaches, “The semiconductor device of claim 16, wherein: the N-type transistors are footers, and the P-type transistors are headers (Van’929, ¶ [0030])”.
Regarding claim 18, Van’929 modified with O'Brien’364 and Jain’127 further teaches, ‘The semiconductor device of claim 17, wherein: the first semiconductor chip is a system semiconductor chip, and the second semiconductor chip is a memory chip (Van’929, ¶ [0030])’,
Regarding claim 19, Van’929 modified with O'Brien’364 and Jain’127 further teaches, “The semiconductor device of claim 18, wherein: the channel portions of the plurality of power gating elements include at least one of MoS2, MoSe₂, MoTe₂, WS₂, WSe2, WTe₂, ZrS₂, ZrSe₂, HfS2, HfSe2, NbSe₂, ReSe2, PtS₂, PtSe₂, PdSe2, PdTe2, VS2, VSe₂, FeSe2, FeTe2, MoS(x)Se(1-x) (wherein 0<x<1), WS(x)Se(1-x) (wherein 0<x<1), Graphene, GaSe, GaTe₂, SnSe, Bi2Se3, Bi2O₂Se, Silicene, Stanene, Tellurene, Borophene and Antimonene” (TMD, O'Brien’364).
Regarding independent claim 20, Van’929 teaches, “A semiconductor device (fig. 1-23; ¶ [0001] - ¶ [0084]) comprising:
((a circuit board which includes circuit wiring;))
a first semiconductor chip which is disposed ((on the circuit board)), the first semiconductor chip including:
a semiconductor substrate (‘semiconductor substrate’, fig. 2; ¶ [0031]) including:
a plurality of circuit elements (‘MOS transistors’, ¶ [0031]); and
a wiring structure which is disposed on the semiconductor substrate, the wiring structure including:
a plurality of wiring layers; and
a plurality of power gating elements (TFTs, ‘power switch circuit (header and/or footer switch)’, ¶ [0031] - ¶ [0032]) disposed in the plurality of wiring layers,
the plurality of power gating elements including N-type transistors and P-type transistors respectively (¶ [0030]) including:
a plurality of channel portions; and
((a second semiconductor chip which is disposed on the first semiconductor chip,
wherein
channel portions of the N-type transistors of the plurality of power gating elements among the plurality of channel portions include a two-dimensional semiconductor material, and
channel portions of the P-type transistors of the plurality of power gating elements among the plurality of channel portions include the two-dimensional semiconductor material or an oxide semiconductor.))
But Van’929 is silent upon the provision of wherein the semiconductor device comprising:
channel portions of the N-type transistors of the plurality of power gating elements among the plurality of channel portions include a two-dimensional semiconductor material, and
channel portions of the P-type transistors of the plurality of power gating elements among the plurality of channel portions include the two-dimensional semiconductor material or an oxide semiconductor.
However, O'Brien’364 teaches a similar device (fig. 2) comprising:
channel portions of the N-type transistors of the plurality of power gating elements among the plurality of channel portions include a two-dimensional semiconductor material, and channel portions of the P-type transistors of the plurality of power gating elements among the plurality of channel portions include the two-dimensional semiconductor material or an oxide semiconductor (fig. 4A-4B; ¶ [0043] - ¶ [0044]).
Van’929 and O'Brien’364 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Van’929 with the features of O'Brien’364 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Van’929 and O'Brien’364 to form the channel using TMD according to the teachings of O'Brien’364 to exploit the advantages of TMD materials, e.g., high mobility, atomic-layer-scale small thickness and high flexibility, transparency, etc.
But Van’929 modified with O'Brien’364 is silent upon the provision of wherein the semiconductor device comprising: a second semiconductor chip which is disposed on the first semiconductor chip.
However, Jain’127 teaches a similar device (fig. 1) comprising: a second semiconductor chip which is disposed on the first semiconductor chip (dies 121, 131, 141 on board 105).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Van’929, O'Brien’364 and Jain’127 to form chip stack on board according to the teachings of Jain’127 as stacking save space and reduce the size of the chip thus saving cost.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
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