DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/27/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
Claims 1-21 have been cancelled. Claims 22-39 have been added. Claims 22-39 are currently pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 22-39 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 8, and 10 of U.S. Patent No. 12,099,454 in view of McWilliams (US 2008/0301256).
As per claims 22-39,
Instant Application
U.S. Patent No. 12,099,454 (US Application 17/556,376)
Claim 22: A method of transferring data in a memory interconnect device, the method comprising: receiving, via a network interconnect, a data request to transfer data from a dynamic random-access memory (DRAM) component of a plurality of DRAM components coupled to the memory interconnect device, wherein the memory interconnect device comprises one or more DRAM controllers, a local interconnect, and a central processing unit (CPU); configuring an engine of the local interconnect to transfer data from the DRAM component responsive to the data request; translating, by the local interconnect, a memory address associated with the data request to generate a translated memory address associated with the DRAM component; sending an access request to the DRAM component, the access request comprising the translated memory address; receiving the data from the DRAM component; and returning the data over the network interconnect in response to the data request.
Claim 8: A method of transferring data in a memory appliance, the method comprising: receiving, from a first server, a data request to transfer data from a memory device of a plurality of memory devices coupled to a local interconnect, wherein the local interconnect is within the memory appliance and is configured to couple the plurality of memory devices to a central processing unit (CPU) of the memory appliance; configuring an engine of the local interconnect to transfer data from the memory device to the first server through a first direct connection responsive to the data request; translating, by the local interconnect, a memory address associated with the data request to generate a translated memory address associated with the memory device; sending an access request to the memory device, the access request comprising the translated memory address; receiving the data from the memory device; and sending the data directly from the local interconnect to the first server in response to the data request.
Note:
Claim 8 of US Patent No. 12,099,454 teaches all of the limitations of instant claim 22 (see the bolded and italicized limitations of claim 8 of US Patent No. 12,099,454) except for the italicized and underlined limitations of instant claim 22.
However, the reference McWilliams (US 2008/0301256) teaches these limitations. See Below.
Claim 23: The method of claim 22, wherein the one or more DRAM controllers are coupled to the plurality of DRAM components and to the local interconnect.
Claim 8 in view of McWilliams.
(See McWilliams: Fig. 1D, Controller 112 (i.e. DRAM controller) coupled to DRAM components 128 and 124 and to CPU complex 109 (i.e. local interconnect))
Claim 24: The method of claim 22, wherein the CPU is coupled to the local interconnect.
Claim 8: A method of transferring data in a memory appliance, the method comprising: receiving, from a first server, a data request to transfer data from a memory device of a plurality of memory devices coupled to a local interconnect, wherein the local interconnect is within the memory appliance and is configured to couple the plurality of memory devices to a central processing unit (CPU) of the memory appliance; configuring an engine of the local interconnect to transfer data from the memory device to the first server through a first direct connection responsive to the data request; translating, by the local interconnect, a memory address associated with the data request to generate a translated memory address associated with the memory device; sending an access request to the memory device, the access request comprising the translated memory address; receiving the data from the memory device; and sending the data directly from the local interconnect to the first server in response to the data request.
Claim 25: The method of claim 22, wherein sending the access request to the DRAM component comprises configuring the one or more DRAM controllers to send the access request to the DRAM component.
Claim 8 in view of McWilliams
(See McWilliams: Fig. 1D, Controller 112 sends access request to the DRAM 124 and 128; Paragraph 1170, memory sub-system controller includes request/response interface 380 to receive requests sent from or forwarded from the other components, and to send responses back to the other components)
Claim 26: The method of claim 22, wherein the data is received from the DRAM component by the one or more DRAM controllers.
Claim 8 in view of McWilliams
(See McWilliams: Fig. 1D, Controller 112 receives data response from the DRAM 124 and 128; Paragraph 1170, memory sub-system controller includes request/response interface 380 to receive requests sent from or forwarded from the other components, and to send responses back to the other components)
Claim 27: The method of claim 26, wherein the data received by the one or more DRAM controllers is received at the local interconnect.
Claim 8 in view of McWilliams
(See McWilliams: Fig. 1D, CPU complex 109 receives the data from controller 112 via link 133; Paragraph 1170, request/response interface 380 includes a bus interface, such as a PCI Express interface, for communication via local connection(s) 130 (as illustrated in FIG. 3B) or link(s) 133)
Claim 28: The method of claim 27, wherein the data returned over the network interconnect is sent from the local interconnect.
Claim 8 in view of McWilliams
(See McWilliams: Figs. 1D and 19, Data is returned to NIC 119 (i.e. network interconnect) from CPU complex 109, see Figure 19; Paragraph 0113, Home node 1906 optionally and/or selectively returns a response to message 1930 to action node 1902. In a first example, if the access is a read access, the response includes data retrieved from memory devices 1950)
Claim 29: The method of claim 22, wherein the network interconnect comprises a PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) ® interconnect.
Claim 10: The method of claim 8, wherein the local interconnect comprises a PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe)@ interconnect.
Claim 30: A memory interconnect device comprising: one or more dynamic random-access memory (DRAM) controllers; a central processing unit (CPU); and a local interconnect configured to couple the one or more DRAM controllers to the CPU of the memory interconnect device, wherein the memory interconnect device is configured to store data within a plurality of DRAM components coupled to the memory interconnect device and to receive a request to access the data in the plurality of DRAM components, and wherein the local interconnect is configured to translate, based on receiving the request, a memory address associated with the request to generate a translated memory address associated with the plurality of DRAM components and access the data stored in the plurality of DRAM components based on the translated memory address.
Claim 1: A system comprising: a memory appliance (MA) comprising a plurality of memory modules and a local interconnect, wherein the local interconnect is within the MA and is configured to couple the plurality of memory modules to a central processing unit (CPU) of the MA, and wherein the MA is configured to store data within the plurality of memory modules and further configured to receive requests to access the data in the MA; a first server directly coupled to the local interconnect of the MA through a first direct connection; and a second server directly coupled to the local interconnect of the MA through a second direct connection, wherein the first server and the second server are configured to send the requests to access the data stored in the MA directly to the local interconnect through the first and second direct connections respectively, and wherein the local interconnect is configured to translate, based on receiving the requests, memory addresses associated with the requests to translated memory addresses associated with the memory modules and access the data stored in the memory modules of the MA based on the translated memory addresses.
Note:
Claim 1 of US Patent No. 12,099,454 teaches all of the limitations of instant claim 30 except for the italicized and underlined limitations.
However, the reference McWilliams (US 2008/0301256) teaches these limitations. See Below.
Claim 31: The memory interconnect device of claim 30, wherein the one or more DRAM controllers are coupled to the plurality of DRAM components and to the local interconnect.
Claim 1 in view of McWilliams
(See McWilliams: Fig. 1D, Controller 112 (i.e. DRAM controller) coupled to DRAM components 128 and 124 and to CPU complex 109 (i.e. local interconnect))
Claim 32: The memory interconnect device of claim 30, wherein the CPU is coupled to the local interconnect.
Claim 1: A system comprising: a memory appliance (MA) comprising a plurality of memory modules and a local interconnect, wherein the local interconnect is within the MA and is configured to couple the plurality of memory modules to a central processing unit (CPU) of the MA, and wherein the MA is configured to store data within the plurality of memory modules and further configured to receive requests to access the data in the MA; a first server directly coupled to the local interconnect of the MA through a first direct connection; and a second server directly coupled to the local interconnect of the MA through a second direct connection, wherein the first server and the second server are configured to send the requests to access the data stored in the MA directly to the local interconnect through the first and second direct connections respectively, and wherein the local interconnect is configured to translate, based on receiving the requests, memory addresses associated with the requests to translated memory addresses associated with the memory modules and access the data stored in the memory modules of the MA based on the translated memory addresses.
Claim 33: The memory interconnect device of claim 30, wherein the local interconnect is to: receive the request via a network interconnect; translate the memory address associated with the request to generate the translated address associated with the plurality of DRAM components; and send an access request to at least one of the plurality of DRAM components, the access request comprising the translated address.
Claim 1 in view of McWilliams
(See McWilliams: Figs. 1D and 19 and Paragraphs 0113 and Paragraph 1199)
Claim 34: The memory interconnect device of claim 33, wherein the local interconnect is further to: receive the data from the at least one of the plurality of DRAM components; and return the data over the network interconnect in response to the request.
Claim 1 in view of McWilliams
(See McWilliams: Fig. 1D, CPU complex 109 returns data to NIC 119)
Claim 35: The memory interconnect device of claim 33, wherein to send the access request to the DRAM component, the local interconnect is to configure the one or more DRAM controllers to send the access request to the DRAM component.
Claim 1 in view of McWilliams
(See McWilliams: Fig. 1D, CPU complex 109 maps address of request and sends request to controller 112 which sends mapped access request to the DRAM 124 and 128; Paragraph 1170, memory sub-system controller includes request/response interface 380 to receive requests sent from or forwarded from the other components, and to send responses back to the other components)
Claim 36: The memory interconnect device of claim 33, wherein the data is received from the at least one of the plurality of DRAM components by the one or more DRAM controllers.
Claim 1 in view of McWilliams
(See McWilliams: Fig. 1D, Controller 112 receives data response from the DRAM 124 and 128; Paragraph 1170, memory sub-system controller includes request/response interface 380 to receive requests sent from or forwarded from the other components, and to send responses back to the other components)
Claim 37: The memory interconnect device of claim 36, wherein the data received by the one or more DRAM controllers is received at the local interconnect.
Claim 1 in view of McWilliams
(See McWilliams: Fig. 1D, CPU complex 109 receives the data from controller 112 via link 133; Paragraph 1170, request/response interface 380 includes a bus interface, such as a PCI Express interface, for communication via local connection(s) 130 (as illustrated in FIG. 3B) or link(s) 133)
Claim 38: The memory interconnect device of claim 34, wherein the data returned over the network interconnect is sent from the local interconnect.
Claim 1 in view of McWilliams
(See McWilliams: Figs. 1D and 19, Data is returned to NIC 119 (i.e. network interconnect) from CPU complex 109, see Figure 19; Paragraph 0113, Home node 1906 optionally and/or selectively returns a response to message 1930 to action node 1902. In a first example, if the access is a read access, the response includes data retrieved from memory devices 1950)
Claim 39: The memory interconnect device of claim 33, wherein the network interconnect comprises a PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe)@ interconnect.
Claim 2: The system of claim 1, wherein the first and second direct connections comprise at least one of a PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) ® connection, an INFINIBAND ® connection, or an Ethernet connection.
Claim 8 of US Patent 12,099,454 discloses a method of receiving data request to access data from a memory device of a plurality of memory devices coupled to a local interconnect, wherein the local interconnect contains an engine to transfer data and the local interconnect is configured to translate the memory address associated with the data request and send the translated memory address with the access request to the memory device to retrieve data, which instant claim 22 also discloses.
Claim 8 of US Patent 12,099,454 does not teach the method comprising a network interconnect receiving the data access request, a DRAM controller, or DRAM components.
These limitations are however known in the art as shown in McWilliams (US 2008/0301256). McWilliams teaches the method comprising receiving, via a network interconnect (Fig. 1D, NIC 119), a data request to transfer data from a dynamic random-access memory (DRAM) component of a plurality of DRAM components coupled to the memory interconnect device (Fig. 1D, Node 148 sends request to transfer data from DRAM 124 and 128 coupled to node 180; Paragraph 0112, a request to access a particular element is sent to a home node of the particular clement. The request includes at least a portion of the respective element identifier of the particular element… Paragraph 0137, respective processors treat all memory as being fine-grained… Paragraph 1150, the fine-grained memory includes one or more of: SRAM, DRAM… Paragraph 1151, the less-fine-grained memory includes one or more of: DRAM), wherein the memory interconnect device comprises one or more DRAM controllers (Fig. 1D, Controller 112 controls DRAM 124 and thus is a DRAM controller; Paragraph 1093, a memory sub-system controller (112), a fine-grained memory (124)… Paragraph 1150, fine-grained memory includes one or more of: SRAM, DRAM… one or more of: the memory sub-system controller includes at least a portion of the fine-grained memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified US Patent 12,099,454’s method of claim 8 to incorporate the teachings of McWilliams and include a network interconnect to receive the data access request, a DRAM controller, and DRAM components in order to provide a high-capacity, high-performance solid-state memory (See McWilliams: Paragraph 0014) while improving the efficiency and speed of memory access requests using inter-node data transfer (See McWilliams: Paragraphs 1304 and 1472).
Instant claim 30 is similar to instant claim 22 and thus instant claim 30 is rejected over the system of claim 1 of US Patent 12,099,454 in view of McWilliams under similar rationale. It would have been obvious to use a memory interconnect device in the system of claim 1 of US Patent 12,099,454 because they are the same embodiment and a memory system is well-known to include memory interconnect device forms to operate in the system.
Dependent claims 23-29 and 31-39 of the instant application are rejected in view of claims 1-2, 8 and 10 of U.S. Patent No. 12,099,454 in view of McWilliams. See Table Above.
Claims 22-39 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 6, 8, and 13-14 of U.S. Patent No. 11,210,240 in view of McWilliams (US 2008/0301256).
As per claims 22-39,
Instant Application
U.S. Patent No. 11,210,240 (US Application 16/595,010)
Claim 22: A method of transferring data in a memory interconnect device, the method comprising: receiving, via a network interconnect, a data request to transfer data from a dynamic random-access memory (DRAM) component of a plurality of DRAM components coupled to the memory interconnect device, wherein the memory interconnect device comprises one or more DRAM controllers, a local interconnect, and a central processing unit (CPU);configuring an engine of the local interconnect to transfer data from the DRAM component responsive to the data request; translating, by the local interconnect, a memory address associated with the data request to generate a translated memory address associated with the DRAM component; sending an access request to the DRAM component, the access request comprising the translated memory address; receiving the data from the DRAM component; and returning the data over the network interconnect in response to the data request.
Claim 6: A method of transferring data in a memory appliance (MA), the method comprising: receiving, from a first server coupled to a local interconnect of the MA through a first connection and from a second server coupled to the local interconnect through a second connection, data requests to transfer data from a plurality of memory devices coupled to the local interconnect, each comprising a memory controller and a memory component, wherein the requests each comprise a respective memory address and are received by the local interconnect through the first and second connections to bypass at least one of a network switch or an interconnect switch disposed external to the MA; configuring an engine of the local interconnect to transfer data from the plurality of memory devices to the first server and the second server through the first and second connections responsive to the data requests; translating, by the engine of the local interconnect, the respective memory addresses associated with the data requests to translated addresses associated with corresponding ones of the plurality of memory modules, while bypassing a host central processing unit (CPU) of the memory appliance, and generate a translated memory address; sending access requests to the plurality of memory devices, the access requests comprising the translated memory addresses; receiving the data from the plurality of memory devices; and sending the data from the local interconnect to the first server and the second server in response to the data requests.
Note:
Claim 6 of US Patent No. 11,210,240 teaches all of the limitations of instant claim 22 (see the bolded and italicized limitations of claim 6 of US Patent No. 11,210,240) except for the italicized and underlined limitations of instant claim 22.
However, the reference McWilliams (US 2008/0301256) teaches these limitations. See Below.
Claim 23: The method of claim 22, wherein the one or more DRAM controllers are coupled to the plurality of DRAM components and to the local interconnect.
Claim 6 in view of McWilliams.
(See McWilliams: Fig. 1D, Controller 112 (i.e. DRAM controller) coupled to DRAM components 128 and 124 and to CPU complex 109 (i.e. local interconnect))
Claim 24: The method of claim 22, wherein the CPU is coupled to the local interconnect.
Claim 6 in view of McWilliams.
(See McWilliams: Fig. 1D, CPU 110 coupled to CPU complex 109 (i.e. the local interconnect))
Claim 25: The method of claim 22, wherein sending the access request to the DRAM component comprises configuring the one or more DRAM controllers to send the access request to the DRAM component.
Claim 6 in view of McWilliams
(See McWilliams: Fig. 1D, Controller 112 sends access request to the DRAM 124 and 128; Paragraph 1170, memory sub-system controller includes request/response interface 380 to receive requests sent from or forwarded from the other components, and to send responses back to the other components)
Claim 26: The method of claim 22, wherein the data is received from the DRAM component by the one or more DRAM controllers.
Claim 6 in view of McWilliams
(See McWilliams: Fig. 1D, Controller 112 receives data response from the DRAM 124 and 128; Paragraph 1170, memory sub-system controller includes request/response interface 380 to receive requests sent from or forwarded from the other components, and to send responses back to the other components)
Claim 27: The method of claim 26, wherein the data received by the one or more DRAM controllers is received at the local interconnect.
Claim 6 in view of McWilliams
(See McWilliams: Fig. 1D, CPU complex 109 receives the data from controller 112 via link 133; Paragraph 1170, request/response interface 380 includes a bus interface, such as a PCI Express interface, for communication via local connection(s) 130 (as illustrated in FIG. 3B) or link(s) 133)
Claim 28: The method of claim 27, wherein the data returned over the network interconnect is sent from the local interconnect.
Claim 6 in view of McWilliams
(See McWilliams: Figs. 1D and 19, Data is returned to NIC 119 (i.e. network interconnect) from CPU complex 109, see Figure 19; Paragraph 0113, Home node 1906 optionally and/or selectively returns a response to message 1930 to action node 1902. In a first example, if the access is a read access, the response includes data retrieved from memory devices 1950)
Claim 29: The method of claim 22, wherein the network interconnect comprises a PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) ® interconnect.
Claim 8: The method of claim 6, wherein the local interconnect is a PERIPHERAL COMPONENT INTERCONNECT EXPRESS (registered trademark) interconnect.
Claim 30: A memory interconnect device comprising: one or more dynamic random-access memory (DRAM) controllers; a central processing unit (CPU); and a local interconnect configured to couple the one or more DRAM controllers to the CPU of the memory interconnect device, wherein the memory interconnect device is configured to store data within a plurality of DRAM components coupled to the memory interconnect device and to receive a request to access the data in the plurality of DRAM components, and wherein the local interconnect is configured to translate, based on receiving the request, a memory address associated with the request to generate a translated memory address associated with the plurality of DRAM components and access the data stored in the plurality of DRAM components based on the translated memory address.
Claim 13: A computing device comprising: a local interconnect comprising a processing engine; a host central processing unit (CPU) coupled to the local interconnect; and a plurality of memory devices coupled to the local interconnect and each comprising a memory controller and a memory component, wherein the computing device is configured to store data within the plurality of memory devices; wherein the processing engine of the local interconnect is configured to: receive requests to access the data from at least one of a first server coupled to the local interconnect of the computing device through a first connection, or a second server coupled to the local interconnect of the computing device through a second connection, wherein the requests to access the data stored in the MA comprise respective addresses and are received by the local interconnect through the first or second connections to bypass at least one of a network switch or an interconnect switch disposed external to the computing device; perform an address translation to translate the respective addresses to translated memory addresses associated with corresponding ones of the plurality of memory modules, while bypassing the host CPU of the MA, to access the data stored in the corresponding ones of the plurality of memory devices responsive to the requests; send access requests to the corresponding ones of the plurality of memory modules, the access requests comprising the translated memory addresses; receive the data from the corresponding ones of the plurality of memory modules; and send the data from the local interconnect to the at least one of the first server and the second server in response to the requests to access the data.
Note:
Claim 13 of US Patent No. 11,210,240 teaches all of the limitations of instant claim 30 except for the italicized and underlined limitations.
However, the reference McWilliams (US 2008/0301256) teaches these limitations. See Below.
Claim 31: The memory interconnect device of claim 30, wherein the one or more DRAM controllers are coupled to the plurality of DRAM components and to the local interconnect.
Claim 13 in view of McWilliams
(See McWilliams: Fig. 1D, Controller 112 (i.e. DRAM controller) coupled to DRAM components 128 and 124 and to CPU complex 109 (i.e. local interconnect))
Claim 32: The memory interconnect device of claim 30, wherein the CPU is coupled to the local interconnect.
Claim 13: A computing device comprising: a local interconnect comprising a processing engine; a host central processing unit (CPU) coupled to the local interconnect; and a plurality of memory devices coupled to the local interconnect and each comprising a memory controller and a memory component, wherein the computing device is configured to store data within the plurality of memory devices; wherein the processing engine of the local interconnect is configured to: receive requests to access the data from at least one of a first server coupled to the local interconnect of the computing device through a first connection, or a second server coupled to the local interconnect of the computing device through a second connection, wherein the requests to access the data stored in the MA comprise respective addresses and are received by the local interconnect through the first or second connections to bypass at least one of a network switch or an interconnect switch disposed external to the computing device; perform an address translation to translate the respective addresses to translated memory addresses associated with corresponding ones of the plurality of memory modules, while bypassing the host CPU of the MA, to access the data stored in the corresponding ones of the plurality of memory devices responsive to the requests; send access requests to the corresponding ones of the plurality of memory modules, the access requests comprising the translated memory addresses; receive the data from the corresponding ones of the plurality of memory modules; and send the data from the local interconnect to the at least one of the first server and the second server in response to the requests to access the data.
Claim 33: The memory interconnect device of claim 30, wherein the local interconnect is to: receive the request via a network interconnect; translate the memory address associated with the request to generate the translated address associated with the plurality of DRAM components; and send an access request to at least one of the plurality of DRAM components, the access request comprising the translated address.
Claim 13 in view of McWilliams
(See McWilliams: Figs. 1D and 19 and Paragraphs 0113 and Paragraph 1199)
Claim 34: The memory interconnect device of claim 33, wherein the local interconnect is further to: receive the data from the at least one of the plurality of DRAM components; and return the data over the network interconnect in response to the request.
Claim 13 in view of McWilliams
(See McWilliams: Fig. 1D, CPU complex 109 returns data to NIC 119)
Claim 35: The memory interconnect device of claim 33, wherein to send the access request to the DRAM component, the local interconnect is to configure the one or more DRAM controllers to send the access request to the DRAM component.
Claim 13 in view of McWilliams
(See McWilliams: Fig. 1D, CPU complex 109 maps address of request and sends request to controller 112 which sends mapped access request to the DRAM 124 and 128; Paragraph 1170, memory sub-system controller includes request/response interface 380 to receive requests sent from or forwarded from the other components, and to send responses back to the other components)
Claim 36: The memory interconnect device of claim 33, wherein the data is received from the at least one of the plurality of DRAM components by the one or more DRAM controllers.
Claim 13 in view of McWilliams
(See McWilliams: Fig. 1D, Controller 112 receives data response from the DRAM 124 and 128; Paragraph 1170, memory sub-system controller includes request/response interface 380 to receive requests sent from or forwarded from the other components, and to send responses back to the other components)
Claim 37: The memory interconnect device of claim 36, wherein the data received by the one or more DRAM controllers is received at the local interconnect.
Claim 13 in view of McWilliams
(See McWilliams: Fig. 1D, CPU complex 109 receives the data from controller 112 via link 133; Paragraph 1170, request/response interface 380 includes a bus interface, such as a PCI Express interface, for communication via local connection(s) 130 (as illustrated in FIG. 3B) or link(s) 133)
Claim 38: The memory interconnect device of claim 34, wherein the data returned over the network interconnect is sent from the local interconnect.
Claim 13 in view of McWilliams
(See McWilliams: Figs. 1D and 19, Data is returned to NIC 119 (i.e. network interconnect) from CPU complex 109, see Figure 19; Paragraph 0113, Home node 1906 optionally and/or selectively returns a response to message 1930 to action node 1902. In a first example, if the access is a read access, the response includes data retrieved from memory devices 1950)
Claim 39: The memory interconnect device of claim 33, wherein the network interconnect comprises a PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe)@ interconnect.
Claim 14: The computing device of claim 13, wherein the first and second connections are selected from the group consisting of PERIPHERAL COMPONENT INTERCONNECT EXPRESS (registered trademark), INFINIBAND (registered trademark), and Ethernet.
Claim 6 of US Patent 11,210,240 discloses a method of receiving data request to access data from a memory device of a plurality of memory devices coupled to a local interconnect, wherein the local interconnect contains an engine to transfer data and the local interconnect is configured to translate the memory address associated with the data request and send the translated memory address with the access request to the memory device to retrieve data, which instant claim 22 also discloses.
Claim 6 of US Patent 11,210,240 does not teach the method comprising a network interconnect receiving the data access request, a DRAM controller, or DRAM components.
These limitations are however known in the art as shown in McWilliams (US 2008/0301256). McWilliams teaches the method comprising receiving, via a network interconnect (Fig. 1D, NIC 119), a data request to transfer data from a dynamic random-access memory (DRAM) component of a plurality of DRAM components coupled to the memory interconnect device (Fig. 1D, Node 148 sends request to transfer data from DRAM 124 and 128 coupled to node 180; Paragraph 0112, a request to access a particular element is sent to a home node of the particular clement. The request includes at least a portion of the respective element identifier of the particular element… Paragraph 0137, respective processors treat all memory as being fine-grained… Paragraph 1150, the fine-grained memory includes one or more of: SRAM, DRAM… Paragraph 1151, the less-fine-grained memory includes one or more of: DRAM), wherein the memory interconnect device comprises one or more DRAM controllers (Fig. 1D, Controller 112 controls DRAM 124 and thus is a DRAM controller; Paragraph 1093, a memory sub-system controller (112), a fine-grained memory (124)… Paragraph 1150, fine-grained memory includes one or more of: SRAM, DRAM… one or more of: the memory sub-system controller includes at least a portion of the fine-grained memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified US Patent 11,210,240’s method of claim 6 to incorporate the teachings of McWilliams and include a network interconnect to receive the data access request, a DRAM controller, and DRAM components in order to provide a high-capacity, high-performance solid-state memory (See McWilliams: Paragraph 0014) while improving the efficiency and speed of memory access requests using inter-node data transfer (See McWilliams: Paragraphs 1304 and 1472).
Instant claim 30 is similar to instant claim 22 and thus instant claim 30 is rejected over the computing device of claim 13 of US Patent 11,210,240 in view of McWilliams under similar rationale. It would have been obvious to have the computing device of claim 13 of US Patent 11,210,240 be a memory interconnect device because they are the same embodiment and a computing device with memory devices and interconnects is well-known to include memory interconnect device forms.
Dependent claims 23-29 and 31-39 of the instant application are rejected in view of claims 6, 8, and 13-14 of U.S. Patent No. 11,210,240 in view of McWilliams. See Table Above.
Claims 22-39 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 6, and 8 of U.S. Patent No. 10,437,747 in view of McWilliams (US 2008/0301256).
As per claims 22-39,
Instant Application
U.S. Patent No. 10,437,747 (US Application 15/096,111)
Claim 22: A method of transferring data in a memory interconnect device, the method comprising: receiving, via a network interconnect, a data request to transfer data from a dynamic random-access memory (DRAM) component of a plurality of DRAM components coupled to the memory interconnect device, wherein the memory interconnect device comprises one or more DRAM controllers, a local interconnect, and a central processing unit (CPU);configuring an engine of the local interconnect to transfer data from the DRAM component responsive to the data request; translating, by the local interconnect, a memory address associated with the data request to generate a translated memory address associated with the DRAM component; sending an access request to the DRAM component, the access request comprising the translated memory address; receiving the data from the DRAM component; and returning the data over the network interconnect in response to the data request.
Claim 6: A method of transferring data in a memory appliance, the method comprising: receiving, from a first server, a data request to transfer data from a memory device of a plurality of memory devices coupled to a local interconnect; configuring an engine of the local interconnect to transfer data from the memory device to the first server through a first direct connection responsive to the data request; translating, by the local interconnect, a memory address associated with the data request to bypass a host central processing unit (CPU) of the memory appliance and generate a translated memory address; sending an access request to the memory device, the access request comprising the translated memory address; receiving the data from the memory device; and sending the data directly from the local interconnect to the first server in response to the data request.
Note:
Claim 6 of US Patent No. 10,437,747 teaches all of the limitations of instant claim 22 (see the bolded and italicized limitations of claim 6 of US Patent No. 10,437,747) except for the italicized and underlined limitations of instant claim 22.
However, the reference McWilliams (US 2008/0301256) teaches these limitations. See Below.
Claim 23: The method of claim 22, wherein the one or more DRAM controllers are coupled to the plurality of DRAM components and to the local interconnect.
Claim 6 in view of McWilliams.
(See McWilliams: Fig. 1D, Controller 112 (i.e. DRAM controller) coupled to DRAM components 128 and 124 and to CPU complex 109 (i.e. local interconnect))
Claim 24: The method of claim 22, wherein the CPU is coupled to the local interconnect.
Claim 6 in view of McWilliams.
(See McWilliams: Fig. 1D, CPU 110 coupled to CPU complex 109 (i.e. the local interconnect))
Claim 25: The method of claim 22, wherein sending the access request to the DRAM component comprises configuring the one or more DRAM controllers to send the access request to the DRAM component.
Claim 6 in view of McWilliams
(See McWilliams: Fig. 1D, Controller 112 sends access request to the DRAM 124 and 128; Paragraph 1170, memory sub-system controller includes request/response interface 380 to receive requests sent from or forwarded from the other components, and to send responses back to the other components)
Claim 26: The method of claim 22, wherein the data is received from the DRAM component by the one or more DRAM controllers.
Claim 6 in view of McWilliams
(See McWilliams: Fig. 1D, Controller 112 receives data response from the DRAM 124 and 128; Paragraph 1170, memory sub-system controller includes request/response interface 380 to receive requests sent from or forwarded from the other components, and to send responses back to the other components)
Claim 27: The method of claim 26, wherein the data received by the one or more DRAM controllers is received at the local interconnect.
Claim 6 in view of McWilliams
(See McWilliams: Fig. 1D, CPU complex 109 receives the data from controller 112 via link 133; Paragraph 1170, request/response interface 380 includes a bus interface, such as a PCI Express interface, for communication via local connection(s) 130 (as illustrated in FIG. 3B) or link(s) 133)
Claim 28: The method of claim 27, wherein the data returned over the network interconnect is sent from the local interconnect.
Claim 6 in view of McWilliams
(See McWilliams: Figs. 1D and 19, Data is returned to NIC 119 (i.e. network interconnect) from CPU complex 109, see Figure 19; Paragraph 0113, Home node 1906 optionally and/or selectively returns a response to message 1930 to action node 1902. In a first example, if the access is a read access, the response includes data retrieved from memory devices 1950)
Claim 29: The method of claim 22, wherein the network interconnect comprises a PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) ® interconnect.
Claim 8: The method of claim 6, wherein the local interconnect is a peripheral component interconnect express (PCIe) interconnect.
Claim 30: A memory interconnect device comprising: one or more dynamic random-access memory (DRAM) controllers; a central processing unit (CPU); and a local interconnect configured to couple the one or more DRAM controllers to the CPU of the memory interconnect device, wherein the memory interconnect device is configured to store data within a plurality of DRAM components coupled to the memory interconnect device and to receive a request to access the data in the plurality of DRAM components, and wherein the local interconnect is configured to translate, based on receiving the request, a memory address associated with the request to generate a translated memory address associated with the plurality of DRAM components and access the data stored in the plurality of DRAM components based on the translated memory address.
Claim 1: A system comprising: a memory appliance (MA) comprising a plurality of memory modules and a local interconnect, wherein the MA is configured to store data within the plurality of memory modules and further configured to receive requests to access the data; a first server directly coupled to the local interconnect of the MA through a first direct connection; a second server directly coupled to the local interconnect of the MA through a second direct connection; wherein the first server and the second server are configured to access the data stored in the MA through the first and second direct connections to the MA, wherein the first server and the second server are configured to send the requests to access the data stored in the MA to the local interconnect through the first and second direct connections and without sending the requests over a network switch or an interconnect switch disposed external to the memory appliance; and wherein the first server and the second server are configured to send the requests to access the data stored in the MA directly to the local interconnect through the first and second direct connections, the local interconnect to perform an address translation to bypass a host central processing unit (CPU) of the memory appliance and access the data stored in the MA responsive to the requests.
Note:
Claim 1 of US Patent No. 10,437,747 teaches all of the limitations of instant claim 30 except for the italicized and underlined limitations.
However, the reference McWilliams (US 2008/0301256) teaches these limitations. See Below.
Claim 31: The memory interconnect device of claim 30, wherein the one or more DRAM controllers are coupled to the plurality of DRAM components and to the local interconnect.
Claim 1 in view of McWilliams
(See McWilliams: Fig. 1D, Controller 112 (i.e. DRAM controller) coupled to DRAM components 128 and 124 and to CPU complex 109 (i.e. local interconnect))
Claim 32: The memory interconnect device of claim 30, wherein the CPU is coupled to the local interconnect.
Claim 1 in view of McWilliams.
(See McWilliams: Fig. 1D, CPU 110 coupled to CPU complex 109 (i.e. the local interconnect))
Claim 33: The memory interconnect device of claim 30, wherein the local interconnect is to: receive the request via a network interconnect; translate the memory address associated with the request to generate the translated address associated with the plurality of DRAM components; and send an access request to at least one of the plurality of DRAM components, the access request comprising the translated address.
Claim 1 in view of McWilliams
(See McWilliams: Figs. 1D and 19 and Paragraphs 0113 and Paragraph 1199)
Claim 34: The memory interconnect device of claim 33, wherein the local interconnect is further to: receive the data from the at least one of the plurality of DRAM components; and return the data over the network interconnect in response to the request.
Claim 1 in view of McWilliams
(See McWilliams: Fig. 1D, CPU complex 109 returns data to NIC 119)
Claim 35: The memory interconnect device of claim 33, wherein to send the access request to the DRAM component, the local interconnect is to configure the one or more DRAM controllers to send the access request to the DRAM component.
Claim 1 in view of McWilliams
(See McWilliams: Fig. 1D, CPU complex 109 maps address of request and sends request to controller 112 which sends mapped access request to the DRAM 124 and 128; Paragraph 1170, memory sub-system controller includes request/response interface 380 to receive requests sent from or forwarded from the other components, and to send responses back to the other components)
Claim 36: The memory interconnect device of claim 33, wherein the data is received from the at least one of the plurality of DRAM components by the one or more DRAM controllers.
Claim 1 in view of McWilliams
(See McWilliams: Fig. 1D, Controller 112 receives data response from the DRAM 124 and 128; Paragraph 1170, memory sub-system controller includes request/response interface 380 to receive requests sent from or forwarded from the other components, and to send responses back to the other components)
Claim 37: The memory interconnect device of claim 36, wherein the data received by the one or more DRAM controllers is received at the local interconnect.
Claim 1 in view of McWilliams
(See McWilliams: Fig. 1D, CPU complex 109 receives the data from controller 112 via link 133; Paragraph 1170, request/response interface 380 includes a bus interface, such as a PCI Express interface, for communication via local connection(s) 130 (as illustrated in FIG. 3B) or link(s) 133)
Claim 38: The memory interconnect device of claim 34, wherein the data returned over the network interconnect is sent from the local interconnect.
Claim 1 in view of McWilliams
(See McWilliams: Figs. 1D and 19, Data is returned to NIC 119 (i.e. network interconnect) from CPU complex 109, see Figure 19; Paragraph 0113, Home node 1906 optionally and/or selectively returns a response to message 1930 to action node 1902. In a first example, if the access is a read access, the response includes data retrieved from memory devices 1950)
Claim 39: The memory interconnect device of claim 33, wherein the network interconnect comprises a PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe)@ interconnect.
Claim 2: The system of claim 1, wherein the first and second direct connections are selected from the group consisting of Peripheral Component Interconnect Express (PCIe), InfiniBand, and Ethernet.
Claim 6 of US Patent 10,437,747 discloses a method of receiving data request to access data from a memory device of a plurality of memory devices coupled to a local interconnect, wherein the local interconnect contains an engine to transfer data and the local interconnect is configured to translate the memory address associated with the data request and send the translated memory address with the access request to the memory device to retrieve data, which instant claim 22 also discloses.
Claim 6 of US Patent 10,437,747 does not teach the method comprising a network interconnect receiving the data access request, a DRAM controller, or DRAM components.
These limitations are however known in the art as shown in McWilliams (US 2008/0301256). McWilliams teaches the method comprising receiving, via a network interconnect (Fig. 1D, NIC 119), a data request to transfer data from a dynamic random-access memory (DRAM) component of a plurality of DRAM components coupled to the memory interconnect device (Fig. 1D, Node 148 sends request to transfer data from DRAM 124 and 128 coupled to node 180; Paragraph 0112, a request to access a particular element is sent to a home node of the particular clement. The request includes at least a portion of the respective element identifier of the particular element… Paragraph 0137, respective processors treat all memory as being fine-grained… Paragraph 1150, the fine-grained memory includes one or more of: SRAM, DRAM… Paragraph 1151, the less-fine-grained memory includes one or more of: DRAM), wherein the memory interconnect device comprises one or more DRAM controllers (Fig. 1D, Controller 112 controls DRAM 124 and thus is a DRAM controller; Paragraph 1093, a memory sub-system controller (112), a fine-grained memory (124)… Paragraph 1150, fine-grained memory includes one or more of: SRAM, DRAM… one or more of: the memory sub-system controller includes at least a portion of the fine-grained memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified US Patent 10,437,747’s method of claim 6 to incorporate the teachings of McWilliams and include a network interconnect to receive the data access request, a DRAM controller, and DRAM components in order to provide a high-capacity, high-performance solid-state memory (See McWilliams: Paragraph 0014) while improving the efficiency and speed of memory access requests using inter-node data transfer (See McWilliams: Paragraphs 1304 and 1472).
Instant claim 30 is similar to instant claim 22 and thus instant claim 30 is rejected over the system of claim 1 of US Patent 10,437,747 in view of McWilliams under similar rationale. It would have been obvious to use a memory interconnect device in the system of claim 1 of US Patent 10,437,747 because they are the same embodiment and a memory system is well-known to include memory interconnect device forms to operate in the system.
Dependent claims 23-29 and 31-39 of the instant application are rejected in view of claims 1, 2, 6, and 8 of U.S. Patent No. 10,437,747 in view of McWilliams. See Table Above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 22-39 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by McWilliams (US 2008/0301256).
Regarding claim 22, McWilliams teaches a method of transferring data in a memory interconnect device (Fig. 1D, Node 180 performs method of operations of transferring data), the method comprising: receiving, via a network interconnect (Fig. 1D, NIC 119), a data request to transfer data from a dynamic random-access memory (DRAM) component of a plurality of DRAM components (Fig. 1D, DRAM 124 and 128; Paragraph 1150, the fine-grained memory includes one or more of: SRAM, DRAM… Paragraph 1151, the less-fine-grained memory includes one or more of: DRAM) coupled to the memory interconnect device (Fig. 1D, Node 180 (i.e. memory interconnect device) receives data request from node 148 to transfer data from DRAM 124 and 128; Paragraph 0111, a read and/or a write access at a particular one of the nodes to the particular clement is sent to one or more of: the home node… Paragraph 0108, respective clement identifier of the particular clement is mapped and/or translated (such as by software executing on the respective processors and/or by a memory sub-system controller) to a physical address of a memory device), wherein the memory interconnect device comprises one or more DRAM controllers (Fig. 1D, Controller 112 controls DRAM 124 and thus is a DRAM controller; Paragraph 1093, a memory sub-system controller (112), a fine-grained memory (124)… Paragraph 1150, fine-grained memory includes one or more of: SRAM, DRAM… one or more of: the memory sub-system controller includes at least a portion of the fine-grained memory), a local interconnect (Fig. 1D, CPU complex 109 includes bridging 117 to interconnect peripherals, controllers, and switches), and a central processing unit (CPU) (Fig. 1D, CPU 110); configuring an engine of the local interconnect to transfer data from the DRAM component responsive to the data request (Fig. 1D, CPU complex 109 (i.e. local interconnect) contains control processor 359, map/data control 386, and routing unit 213 to route data (i.e. engine); Paragraph 1117, switched and/or routed from a receiving port to a transmitting port by a routing unit (213)… Paragraph 1225, CPU complex 109 (also illustrated in FIG. 1D) includes one or more of the functions of memory sub-system controller 112 and/or of switch 116, including map/data control 386, cache control 382, page/block control 378, sequential write control 384, ACID functional unit 344, locking logic 345, compress/decompress 370, dictionaries 371, data copy logic 379, routing unit 213, and control processor 359); translating, by the local interconnect, a memory address associated with the data request to generate a translated memory address associated with the DRAM component (Fig. 2D, Map/data control 386 of CPU complex 109 (i.e. local interconnect) translates addresses associated with DRAM; Paragraph 0108, home node uses the at least a portion of the respective element identifier in conjunction with the node address space (such as a local map associated with the node address space) to access storage of the particular element); sending an access request to the DRAM component, the access request comprising the translated memory address (Fig. 2D, Map/data control 386 sends the mapped requests to less-fine-grained memory DRAM; Paragraph 1199, map/data control 386 maps respective addresses, such as node addresses, of requests to physical addresses in the less-fine-grained memory); receiving the data from the DRAM component (Fig. 3B, DRAM controller receives response data from less-fine-grained memory interface 376 and returns it to CPU complex 109; Paragraph 1170, memory sub-system controller includes request/response interface 380 to receive requests sent from or forwarded from the other components, and to send responses back to the other components); and returning the data over the network interconnect in response to the data request (Fig. 19, Data from read is returned to other nodes in a response; Paragraph 0113, Home node 1906 optionally and/or selectively returns a response to message 1930 to action node 1902. In a first example, if the access is a read access, the response includes data retrieved from memory devices 1950).
Regarding claim 23, McWilliams teaches the method of claim 22. McWilliams teaches the method comprising wherein the one or more DRAM controllers are coupled to the plurality of DRAM components and to the local interconnect (Fig. 1D, Controller 112 (i.e. DRAM controller) coupled to DRAM components 128 and 124 and to CPU complex 109 (i.e. local interconnect)).
Regarding claim 24, McWilliams teaches the method of claim 22. McWilliams teaches the method comprising wherein the CPU is coupled to the local interconnect (Fig. 1D, CPU 110 coupled as part of CPU complex 109).
Regarding claim 25, McWilliams teaches the method of claim 22. McWilliams teaches the method comprising wherein sending the access request to the DRAM component comprises configuring the one or more DRAM controllers to send the access request to the DRAM component (Fig. 1D, Controller 112 sends access request to the DRAM 124 and 128; Paragraph 1170, memory sub-system controller includes request/response interface 380 to receive requests sent from or forwarded from the other components, and to send responses back to the other components).
Regarding claim 26, McWilliams teaches the method of claim 22. McWilliams teaches the method comprising wherein the data is received from the DRAM component by the one or more DRAM controllers (Fig. 1D, Controller 112 receives data response from the DRAM 124 and 128; Paragraph 1170, memory sub-system controller includes request/response interface 380 to receive requests sent from or forwarded from the other components, and to send responses back to the other components).
Regarding claim 27, McWilliams teaches the method of claim 26. McWilliams teaches the method comprising wherein the data received by the one or more DRAM controllers is received at the local interconnect (Fig. 1D, CPU complex 109 receives the data from controller 112 via link 133; Paragraph 1170, request/response interface 380 includes a bus interface, such as a PCI Express interface, for communication via local connection(s) 130 (as illustrated in FIG. 3B) or link(s) 133).
Regarding claim 28, McWilliams teaches the method of claim 27. McWilliams teaches the method comprising wherein the data returned over the network interconnect is sent from the local interconnect (Figs. 1D and 19, Data is returned to NIC 119 (i.e. network interconnect) from CPU complex 109, see Figure 19; Paragraph 0113, Home node 1906 optionally and/or selectively returns a response to message 1930 to action node 1902. In a first example, if the access is a read access, the response includes data retrieved from memory devices 1950).
Regarding claim 29, McWilliams teaches the method of claim 22. McWilliams teaches the method comprising wherein the network interconnect comprises a PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) ® interconnect (Fig. 1D, NIC 119 uses PCIe; Paragraph 1100, NIC(s) 119 are coupled to CPU complex 109 via one or more PCI Express link(s) (such as link(s) 135)).
Regarding claim 30, McWilliams teaches a memory interconnect device (Fig. 1D, Node 180) comprising: one or more dynamic random-access memory (DRAM) controllers (Fig. 1D, Controller 112 controls DRAM 124 and thus is a DRAM controller; Paragraph 1093, a memory sub-system controller (112), a fine-grained memory (124)… Paragraph 1150, fine-grained memory includes one or more of: SRAM, DRAM… one or more of: the memory sub-system controller includes at least a portion of the fine-grained memory); a central processing unit (CPU) (Fig. 1D, CPU 110); and a local interconnect configured to couple the one or more DRAM controllers to the CPU of the memory interconnect device (Fig. 1D, CPU complex 109 includes bridging 117 to interconnect peripherals, controllers, switches, and CPU 110), wherein the memory interconnect device is configured to store data within a plurality of DRAM components coupled to the memory interconnect device and to receive a request to access the data in the plurality of DRAM components (Fig. 1D, Node 148 sends request to access data from DRAM 124 and 128 coupled to node 180; Paragraph 0112, a request to access a particular element is sent to a home node of the particular clement. The request includes at least a portion of the respective element identifier of the particular element… Paragraph 0137, respective processors treat all memory as being fine-grained… Paragraph 1150, the fine-grained memory includes one or more of: SRAM, DRAM… Paragraph 1151, the less-fine-grained memory includes one or more of: DRAM), and wherein the local interconnect is configured to translate, based on receiving the request, a memory address associated with the request to generate a translated memory address associated with the plurality of DRAM components (Fig. 2D, Map/data control 386 of CPU complex 109 (i.e. local interconnect) translates addresses associated with DRAM; Paragraph 0108, home node uses the at least a portion of the respective element identifier in conjunction with the node address space (such as a local map associated with the node address space) to access storage of the particular element… Paragraph 1200, map/data control 386 maps respective addresses of the read requests to physical addresses in the less-fine-grained memory, and forwards the requests (using the physical addresses) to less-fine-grained memory interface 376); and access the data stored in the plurality of DRAM components based on the translated memory address (Fig. 19, Data from read is returned to other nodes in a response based on the translated address 1945; Paragraph 0113, look-up in local map 1940 produces physical address 1945 which is used to access memory devices 1950 at home node 1906… if the access is a read access, the response includes data retrieved from memory devices 1950).
Regarding claim 31, McWilliams teaches the memory interconnect device of claim 30. McWilliams teaches the memory interconnect device comprising wherein the one or more DRAM controllers are coupled to the plurality of DRAM components and to the local interconnect (Fig. 1D, Controller 112 (i.e. DRAM controller) coupled to DRAM components 128 and 124 and to CPU complex 109 (i.e. local interconnect)).
Regarding claim 32, McWilliams teaches the memory interconnect device of claim 30. McWilliams teaches the memory interconnect device comprising wherein the CPU is coupled to the local interconnect (Fig. 1D, CPU 110 coupled as part of CPU complex 109).
Regarding claim 33, McWilliams teaches the memory interconnect device of claim 30. McWilliams teaches the memory interconnect device comprising wherein the local interconnect is to: receive the request via a network interconnect (Figs. 1D and 19, NIC 119 (i.e. network interconnect) receives request from external node and sends it to CPU complex 109 (i.e. local interconnect), as seen in Figure 19, 1935; Paragraph 0113, portion of message 1930 sent (1935) to home node 1906); translate the memory address associated with the request to generate the translated address associated with the plurality of DRAM components (Figs. 2D and 19, CPU complex 109 has map/data control 386 which is used to map the address as seen in Figure 19, 1940; Paragraph 0113, At least a portion of element identifier 1910 is used as part of a look-up in local map 1940 at home node 1906. The look-up in local map 1940 produces physical address 1945 which is used to access memory devices 1950 at home node 1906); and send an access request to at least one of the plurality of DRAM components, the access request comprising the translated address (Fig. 19, Mapped access request sent to DRAM component 1950; Paragraph 1199, map/data control 386 maps respective addresses, such as node addresses, of requests to physical addresses in the less-fine-grained memory).
Regarding claim 34, McWilliams teaches the memory interconnect device of claim 33. McWilliams teaches the memory interconnect device comprising wherein the local interconnect is further to: receive the data from the at least one of the plurality of DRAM components (Fig. 1D, CPU complex 109 receives data from DRAM 124 and 128); and return the data over the network interconnect in response to the request (Fig. 1D, CPU complex 109 returns data to NIC 119).
Regarding claim 35, McWilliams teaches the memory interconnect device of claim 33. McWilliams teaches the memory interconnect device comprising wherein to send the access request to the DRAM component, the local interconnect is to configure the one or more DRAM controllers to send the access request to the DRAM component (Fig. 1D, CPU complex 109 maps address of request and sends request to controller 112 which sends mapped access request to the DRAM 124 and 128; Paragraph 1170, memory sub-system controller includes request/response interface 380 to receive requests sent from or forwarded from the other components, and to send responses back to the other components).
Regarding claim 36, McWilliams teaches the memory interconnect device of claim 33. McWilliams teaches the memory interconnect device comprising wherein the data is received from the at least one of the plurality of DRAM components by the one or more DRAM controllers (Fig. 1D, Controller 112 receives data response from the DRAM 124 and 128; Paragraph 1170, memory sub-system controller includes request/response interface 380 to receive requests sent from or forwarded from the other components, and to send responses back to the other components).
Regarding claim 37, McWilliams teaches the memory interconnect device of claim 36. McWilliams teaches the memory interconnect device comprising wherein the data received by the one or more DRAM controllers is received at the local interconnect (Fig. 1D, CPU complex 109 receives the data from controller 112 via link 133; Paragraph 1170, request/response interface 380 includes a bus interface, such as a PCI Express interface, for communication via local connection(s) 130 (as illustrated in FIG. 3B) or link(s) 133).
Regarding claim 38, McWilliams teaches the memory interconnect device of claim 34. McWilliams teaches the memory interconnect device comprising wherein the data returned over the network interconnect is sent from the local interconnect (Figs. 1D and 19, Data is returned to NIC 119 (i.e. network interconnect) from CPU complex 109, see Figure 19; Paragraph 0113, Home node 1906 optionally and/or selectively returns a response to message 1930 to action node 1902. In a first example, if the access is a read access, the response includes data retrieved from memory devices 1950).
Regarding claim 39, McWilliams teaches the memory interconnect device of claim 33. McWilliams teaches the memory interconnect device comprising wherein the network interconnect comprises a PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) ® interconnect (Fig. 1D, NIC 119 uses PCIe; Paragraph 1100, NIC(s) 119 are coupled to CPU complex 109 via one or more PCI Express link(s) (such as link(s) 135)).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PGPUB 2012/0311232 to Portfield discloses a memory controller that contains a switch coupled to a host-memory translation circuit which performs memory translation to access a DRAM memory coupled to a DRAM controller.
US PGPUB 2015/0067229 to Connor discloses a NUMA node PCIe switch that receives memory access request and performs address mapping on the requests to send to PCIe devices.
US Patent 7,962,715 to Ware discloses a mapping module that translates virtual addresses to physical addresses that access a DRAM.
US PGPUB 2007/0180041 to Suzuoki discloses a memory multi-processor that translates network addresses to memory addresses of the memory.
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/H.Z.W./Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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