Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/30/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 700 of figure 7. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 13 is objected to because of the following informalities: claim recites "...transmitting the transformed data to the host device. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8, 9 and 14 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation "the load balancing" in line 14. There is insufficient antecedent basis for this limitation in the claim. For examination purposes the examiner has assumed that “the load balancing” should instead be “the load balancing operation”.
Claim 9 recites the limitation "the load balancing" in line 18. There is insufficient antecedent basis for this limitation in the claim. For examination purposes the examiner has assumed that “the load balancing” should instead be “the load balancing operation”.
Claim 14 recites the limitation "the load balancing" in line 7. There is insufficient antecedent basis for this limitation in the claim. For examination purposes the examiner has assumed that “the load balancing” should instead be “the load balancing operation”.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim1-7 and 9-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Per Step 1: Claim 1 is directed to “A method comprising…” steps which is directed to a process, therefore one of the four statutory categories
Per Step 2A, Prong 1: Claim 1 recites the limitation:
performing a load balancing operation to select a first container of a plurality of containers to store a first command address;
The above emphasized limitation can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process as well as a mathematical concept.
Accordingly, claim 1 recites a judicial exception (i.e. abstract idea).
Per Step 2A Prong B:
The additional elements recited in claim 1 include:
obtaining a plurality of command requests, each comprising a command address of a plurality of command addresses;
storing the first command address in the first container;
transmitting the first command address from the first container to a data transform accelerator; and
obtaining transformed data from the data transform accelerator.
Regarding the additional element (i), the limitation recited amounts to insignificant extra-solution activity of necessary data gathering/sending/outputting, as it merely gathering/sending/outputting data for the judicial exception, which is not indicative of integration into a practical application. See MPEP 2106.04(d) and 2106.05(g)
Regarding the additional element (ii), the limitation recited amounts to insignificant extra-solution activity of necessary data gathering/sending/outputting, as it merely gathering/sending/outputting data for the judicial exception, which is not indicative of integration into a practical application. See MPEP 2106.04(d) and 2106.05(g)
Regarding the additional element (iii), the limitation recited amounts to insignificant extra-solution activity of necessary data gathering/sending/outputting, as it merely gathering/sending/outputting data for the judicial exception, which is not indicative of integration into a practical application; mere instructions are to implement the limitations which can be performed in the human mind i.e., the judicial exception, on a computer which is not indicative of integration into a practical application. See MPEP 2106.04(d) and 2106.05(e, f, g, h)
Regarding the additional element (iv), the limitation recited amounts to insignificant extra-solution activity of necessary data gathering/sending/outputting, as it merely gathering/sending/outputting data for the judicial exception, which is not indicative of integration into a practical application; is mere instructions to implement the limitations which can be performed in the human mind i.e., the judicial exception, on a computer which is not indicative of integration into a practical application. See MPEP 2106.04(d) and 2106.05(e, f, g, h)
Furthermore, the combination of additional elements results in mere instructions to implement the exception on a computer and data gathering/outputting/sending steps which is insignificant extra-solution activity. This combination of additional elements fails to integrate the judicial exception into a practical application. See MPEP 2106.04(d).
Per Step 2B:
Regarding the additional element (i), the limitation recited amounts to insignificant extra-solution activity of data gathering, as it is merely gathering data for the use of the judicial exception, which is not indicative or integration into a practical application. Further, the additional element (i) is receiving or transmitting data over a network which is well-understood, routine, and conventional activity. See MPEP 2106.05(d). The courts have found adding extra-solution activity and well-understood, routine, and conventional activity is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.05(a, g)
Regarding the additional element (ii), the limitation recited amounts to insignificant extra-solution activity of data storing, as it is merely storing data in a location specified by the judicial exception, which is not indicative or integration into a practical application. Further, the additional element (i) is storing and retrieving information in memory which is well-understood, routine, and conventional activity. See MPEP 2106.05(d). The courts have found adding extra-solution activity and well-understood, routine, and conventional activity is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.05(a, g)
Regarding the additional element (iii), the limitation recited amounts to insignificant extra-solution activity of data sending, as it is merely sending data, which is not indicative or integration into a practical application. Further, the additional element (i) is transmitting data over a network which is well-understood, routine, and conventional activity. See MPEP 2106.05(d). The courts have found adding extra-solution activity and well-understood, routine, and conventional activity is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.05(a, g)
Regarding the additional element (iv), the limitation recited amounts to insignificant extra-solution activity of data gathering, as it is merely gathering data from a computer component, which is not indicative or integration into a practical application. Further, the additional element (i) is receiving data over a network which is well-understood, routine, and conventional activity. See MPEP 2106.05(d). The courts have found adding extra-solution activity and well-understood, routine, and conventional activity is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.05(a, g)
The combination of these additional elements amounts to a method comprising steps which can be performed mentally implemented by generic computer function with mere instructions to apply the abstract idea on a computer, and comprising steps of insignificant extra-solution and well-understood, routine, and conventional activity.
Therefore, the additional elements, when considered individually and in combination, fail to add an inventive concept to the claim.
Consequently claim 1 as a whole does not amount to significantly more than the recited judicial exception and the claim is not eligible.
Claim 2 is dependent on claim 1, and therefore inherits the same judicial exception as claim 1.
Further claim 2 recites
further comprises in response to obtaining the transformed data, removing the first command address from the first container
Per Step 2A and 2B:
Limitation (i) amounts to mere data processing steps which is insignificant extra-solution activity. This additional element of insignificant extra-solution activity is not indicative of integration into a practical application. Even when considered in combination with the additional elements of claim 1, the additional elements comprise mere instructions to apply the exception and insignificant extra-solution activity, which are not indicative of integration into a practical application.
This additional element of extra solution activity is further considered to be the well-understood, routine and conventional activity identified by the courts of deleting data records as seen in Whitserve LLC v. Dropbox, Inc. This additional element is not enough to amount to significantly more than the recited judicial exceptions. Even when considered in combination with the additional elements of claim 1, the additional elements do not provide an inventive concept and do not amount to significantly more than the recited judicial exceptions. Thus claim 2 is not eligible.
Claim 3 is dependent of claim, and therefore inherits the same judicial exception as claim 1.
Further claim 3 recites
[…] generate a command request of the plurality of command requests
which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and therefore reciting a mental process.
The additional elements of claim 3 include:
wherein the plurality of command requests are generated by one or more software applications,
wherein each software application comprises one or more threads, each thread operable to…
Per Step 2A and 2B:
Regarding limitation (i), it states mere instructions to implement the limitation which can be performed in the human mind i.e., the judicial exception on a computer, which is not indicative of integration into a practical application and are merely adding words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea. The courts have found adding mere instructions to apply the exceptions is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.04(d) and 2106.05(f).
Regarding limitation (ii), it states merely indicating a field of use or technological environment in which to apply a judicial exception. Further, the courts have found merely employing generic computer functions to execute an abstract idea, even when limiting the use of the idea to one particular environment, does not add significantly more. See MPEP 2106.05(h).
Therefore, the additional elements amount to mere instructions to apply the judicial exception in a computer environment and indicating a field of use or technological environment which when considered individually and in combination, fail to add an inventive concept to the claim and do not amount to significantly more than the judicial exceptions. Therefore claim 3 is ineligible
Claim 4 is dependent of claim 1, and therefore inherits the same judicial exception as claim 1.
Further claim 4 recites:
[…] performs a data transform operation to the first input data using the first command which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and therefore reciting a mental process.
The additional element of claim 4 includes:
wherein the data transform accelerator
wherein the first command address points to a first command and first input data
Per Step 2A and 2B:
Regarding limitation (i), it states mere instructions to implement the limitation which can be performed in the human mind i.e., the judicial exception on a computer, which is not indicative of integration into a practical application and are merely adding words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea. The courts have found adding mere instructions to apply the exceptions is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.04(d) and 2106.05(f).
Regarding limitation (ii), it further limits the receiving data over a network “obtaining a plurality of command requests, each comprising a command address of a plurality of command addresses; ”, as recited in claim 1, which is merely insignificant extra solution activity and well understood routine and conventional as stated in arguments made for claim 1.
Therefore, the additional elements amount to insignificant extra-solution activity and mere instruction to apply, which when considered individually and in combination, fail to add an inventive concept to the claim and do not amount to significantly more than the judicial exception. Therefore claim 4 is ineligible
Claim 5 is dependent of claim 4, and therefore inherits the same judicial exception as claim 4.
Further claim 5 recites
wherein the first input data comprises source data, metadata, and additional data, the additional data comprising one or more of an initialization vector for encryption or decryption, method authentication code, and authentication data for encryption or decryption
Per Step 2A and 2B:
Regarding limitation (i), it further limits “wherein the first command address points to a first command and first input data” from claim 4 which limits “obtaining…” from claim 1 which has been found to be insignificant extra solution activity. Thus, the limitation in claim 5 is merely insignificant extra solution activity and well understood routine and conventional as stated in arguments made for claim 4 and therefore claim 1.
Therefore, the additional elements amount to insignificant extra solution activity, which when considered individually and in combination, fail to add an inventive concept to the claim and do not amount to significantly more than the judicial exception. Therefore claim 5 is ineligible
Claim 6 is dependent of claim 1, and therefore inherits the same judicial exception as claim 1.
Further claim 6 recites
wherein the plurality of containers are command pointer rings to store the plurality of command addresses
Per Step 2A and 2B:
Regarding limitation (i), it states merely indicating a field of use or technological environment in which to apply a judicial exception. Further, the courts have found merely employing generic computer functions to execute an abstract idea, even when limiting the use of the idea to one particular environment, does not add significantly more. See MPEP 2106.05(h).
Therefore, the additional elements, when considered individually and in combination, fail to add an inventive concept to the claim and do not amount to significantly more than the judicial exception. Therefore claim 6 is ineligible
Claim 7 is dependent on claim 1, and therefore inherits the same judicial exception as claim 1.
Further claim 7 recites
wherein […] stores the first command address in the first container
[…] stores a second command address in a second container
a first software application and a second software application
Per Step 2A and Step 2B:
Regarding the additional element (i), the limitation recited amounts to mere data processing steps which is found to be insignificant extra-solution as it is merely storing data in a location specified by the judicial exception, which is not indicative or integration into a practical application. Further, the additional element (i) is storing and retrieving information in memory which is well-understood, routine, and conventional activity. See MPEP 2106.05(d). The courts have found adding extra-solution activity and well-understood, routine, and conventional activity is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.05(a, g)
Regarding the additional element (ii), the limitation recited amounts to mere data processing steps which is found to be insignificant extra-solution as it is merely storing data in a location specified by the judicial exception, which is not indicative or integration into a practical application. Further, the additional element (ii) is storing and retrieving information in memory which is well-understood, routine, and conventional activity. See MPEP 2106.05(d). The courts have found adding extra-solution activity and well-understood, routine, and conventional activity is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.05(a, g)
Regarding limitation element (iii), the limitation recited amounts to merely indicating a field of use or technological environment in which to apply a judicial exception. Further the courts have found that employing generic computer functions to execute an abstract idea, even when limiting the use of the idea to one particular environment, does not add significantly more. See MPEP 2106.05(h)
Therefore, the additional elements amount to insignificant extra-solution activity and merely indicating a field of use or technological environment, which when considered individually and in combination, fail to add an inventive concept to the claim and do not amount to significantly more than the judicial exception. Therefore claim 7 is ineligible
Claim 9 is dependent on claim 1, and therefore inherits the same judicial exception as claim 1.
Further claim 9 recites
wherein the load balancing is performed according to a class of service, and the load balancing uses at least one of a round-robin method, a queue depth method, or a CPU core ring method
which further limits the judicial exception of claim 1 and can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process.
Accordingly, for the same reasons presented with respect to claim 1, the additional elements are not indicative of integration into a practical application, nor do they amount to significantly more than the recited judicial exceptions. Thus claim 9 is not eligible.
Claim 10 is dependent on claim 1, and therefore inherits the same judicial exception as claim 1.
Further claim 10 recites
wherein the first container is locked for mutual exclusion prior to storing the first command address in the first container,
and the first container is unlocked after storing the first command address in the first container.
Per Step 2A and 2B:
Regarding limitation (i), a mutual exclusion locking/un-locking mechanisms have been found to be insignificant extra solution activity as well as well-understood, routine and conventional by the courts as found in TS Patents LLC v. Yahoo! Inc. and US 8799473 states that a locking mechanism is conventional page 10 col 3 lines 16-22.
Regarding limitation (i), a mutual exclusion locking/un-locking mechanisms have been found to be insignificant extra solution activity as well as well-understood, routine and conventional by the courts as found in TS Patents LLC v. Yahoo! Inc. and US 8799473 states that a locking mechanism is conventional page 10 col 3 lines 16-22.
Accordingly the additional elements amount to insignificant extra solution activity, which when considered individually or in combination are not indicative of integration into a practical application, nor do they amount to significantly more than the recited judicial exceptions. Thus claim 10 is not eligible.
Claim 11 is dependent on claim 1, and therefore inherits the same judicial exception as claim 1.
Further claim 11 recites
wherein a first set of containers of the plurality of containers is associated with a first data transform accelerator,
such that a first set of command addresses stored in the first set of containers are transmitted to the first data transform accelerator and are not transmitted to a second data transform accelerator.
Per Step 2A and 2B:
Regarding limitation (i), it states mere instructions to implement the limitation which can be performed in the human mind i.e., the judicial exception on a computer, which is not indicative of integration into a practical application and are merely adding words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea. The courts have found adding mere instructions to apply the exceptions is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.04(d) and 2106.05(f).
Regarding the additional element (ii), the limitation recited amounts to mere data processing steps which is found to be insignificant extra-solution as it is merely storing data in a location specified by the judicial exception, which is not indicative or integration into a practical application. Further, the additional element (ii) is storing and retrieving information in memory which is well-understood, routine, and conventional activity. See MPEP 2106.05(d). The courts have found adding extra-solution activity and well-understood, routine, and conventional activity is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.05(a, g)
Accordingly the additional elements amount to mere instruction to apply and insignificant extra-solution activity, which when considered individually or in combination are not indicative of integration into a practical application, nor do they amount to significantly more than the recited judicial exceptions. Thus claim 11 is not eligible.
Per Step 1: Claim 12 is directed to “A system, comprising: a host device, comprising: one or more processors; and host software, operated by the one or more processors, to: […] and at least one data transform accelerator to: […],” which is directed to apparatus, therefore one of the four statutory categories
Per Step 2A, Prong 1: Claim 1 recites the limitation:
generate a plurality of command requests, each comprising a plurality of command addresses;
perform a load balancing operation to select a first container of a plurality of containers to store a first command address of the plurality of command addresses;
The above emphasized limitations can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and are therefore reciting a mental process as well as a mathematical concept.
Accordingly, claim 1 recites a judicial exception (i.e. abstract idea).
Per Step 2A Prong B:
The additional elements recited in claim 1 include:
A system, comprising; a host device, comprising: one or more processors; […] and at least one data transform accelerator
and host software, operated by the one or more processors, to:
direct the first command address to be stored in the first container;
and transmit the first command address from the first container;
obtain the first command address transmitted from the first container;
and transmit transformed data to the host device.
Regarding the additional element (i), the limitation recited is mere instructions to implement the limitations which can be performed in the human mind, i.e., the judicial exception, on a computer, which is not indicative of integration into a practical application. See MPEP 2106.04(d) and 2106.0S(f).
Regarding the additional element (ii), the limitation recited is merely indicates a field of use or technological environment in which to apply a judicial exception as employing generic computer functions to execute an abstract idea. See MPEP 2106.05(h)
Regarding the additional element (iii) the limitation recited amounts to insignificant extra-solution activity of necessary data sending, as it merely is sending data directed by the judicial exception, which is not indicative of integration into a practical application. See MPEP 2106.04(d) and 2106.05(g)
Regarding the additional element (iv), the limitation recited amounts to insignificant extra-solution activity of necessary data gathering, as it merely is gathering data from the judicial exception, which is not indicative of integration into a practical application. See MPEP 2106.04(d) and 2106.05(g)
Regarding the additional element (v) the limitation recited amounts to insignificant extra-solution activity of necessary data sending, as it merely is sending data from the judicial exception, which is not indicative of integration into a practical application. See MPEP 2106.04(d) and 2106.05(g)
Regarding the additional element (vi), the limitation recited amounts to insignificant extra-solution activity of necessary data sending, as it merely is sending data from the judicial exception, which is not indicative of integration into a practical application. See MPEP 2106.04(d) and 2106.05(g)
Per Step 2B:
Regarding the additional element (i), the limitation is reciting generic computer components performing steps which can be performed in the human mind, which is mere instructions to apply the exception. The courts have found adding mere instructions to apply the exceptions is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.04(a) and 2106.05(f)
Regarding additional element (ii), the limitation is reciting merely indicating a field of use or technological environment in which to apply a judicial exception. Further, the courts have found merely employing generic computer functions to execute an abstract idea, even when limiting the use of the idea to one particular environment, does not add significantly more. See MPEP 2106.05(h).
Regarding the additional element (iii), the limitation recited amounts to insignificant extra-solution activity of data sending, as it is merely sending data, which is not indicative or integration into a practical application. Further, the additional element (iii) is transmitting data over a network which is well-understood, routine, and conventional activity. See MPEP 2106.05(d). The courts have found adding extra-solution activity and well-understood, routine, and conventional activity is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.05(a, g)
Regarding the additional element (iv), the limitation recited amounts to insignificant extra-solution activity of data sending, as it is merely sending data, which is not indicative or integration into a practical application. Further, the additional element (iv) is transmitting data over a network which is well-understood, routine, and conventional activity. See MPEP 2106.05(d). The courts have found adding extra-solution activity and well-understood, routine, and conventional activity is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.05(a, g)
Regarding the additional element (v), the limitation recited amounts to insignificant extra-solution activity of data gathering, as it is merely gathering data from a computer component, which is not indicative or integration into a practical application. Further, the additional element (i) is receiving data over a network which is well-understood, routine, and conventional activity. See MPEP 2106.05(d). The courts have found adding extra-solution activity and well-understood, routine, and conventional activity is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.05(a, g)
Regarding the additional element (vi), the limitation recited amounts to insignificant extra-solution activity of data sending, as it is merely sending data, which is not indicative or integration into a practical application. Further, the additional element (vi) is transmitting data over a network which is well-understood, routine, and conventional activity. See MPEP 2106.05(d). The courts have found adding extra-solution activity and well-understood, routine, and conventional activity is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.05(a, g)
The combination of these additional elements amounts to mere instructions to apply, mere instructions to implement in a field of use or technological environment, and insignificant extra-solution activity, which individually and in combination do not integrate the judicial exception into a practical application nor do they add an inventive concept to the claim.
Consequently claim 1 as a whole does not amount to significantly more than the recited judicial exception and the claim is not eligible.
Claim 13 is dependent on claim 1, and therefore inherits the same judicial exception as claim 12.
Further claim 13 recites
wherein in response to transmitting the transformed data […], […]consume the first command address from the first container which recites the same limitations as claim 2 and therefore amount to insignificant extra solution activity which is well understood routine and conventional as argued in claim 2.
Additional elements of the host device and the at least one data transform accelerator amount to mere instructions to apply. Therefore the additional elements of claim 13 amount to insignificant extra solution activity and mere instructions to apply, which when considered individually or in combination do not amount to significantly more than the recited judicial exceptions or an integration into a practical application and therefore is ineligible.
Claim 14 is dependent on claim 12, and therefore inherits the same judicial exception as claim 12.
Further claim 14 recites the same limitations as claim 9. Thus for the same reasons as presented in claim 9, claim 14 when considered in combination with claim 12 is directed to an abstract idea without significantly more and is not eligible.
Claim 15 is dependent on claim 12, and therefore inherits the same judicial exception as claim 12.
Further claim 15 recites
perform a data transform operation to the first input data using the first command to generate transformed data which can be performed in the human mind through observation, evaluation, judgement and opinion, with the aid of pen and paper, and therefore reciting a mental process.
The additional element of claim 15 includes:
wherein the at least one data transform accelerator is further to:
obtain a first command associated with the plurality of command requests and first input data using the first command address;
Per Step 2A and Step 2B:
Regarding limitation (i), it states mere instructions to implement the limitation which can be performed in the human mind i.e., the judicial exception on a computer, which is not indicative of integration into a practical application and are merely adding words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea. The courts have found adding mere instructions to apply the exceptions is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.04(d) and 2106.05(f).
Regarding the additional element (ii), the limitation recited amounts to mere data processing steps which is found to be insignificant extra-solution as it is merely gathering data from the judicial exception, which is not indicative or integration into a practical application. Further, the additional element (ii) retrieving information in memory which is well-understood, routine, and conventional activity. See MPEP 2106.05(d). The courts have found adding extra-solution activity and well-understood, routine, and conventional activity is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.05(a, g)
Accordingly the additional elements amount to mere instruction to apply and insignificant extra-solution activity, which when considered individually or in combination are not indicative of integration into a practical application, nor do they amount to significantly more than the recited judicial exceptions. Thus claim 15 is not eligible.
Claim 16 is dependent on claim 15, and therefore inherits the same judicial exception as claim 15.
Further claim 16 recites the same limitations as claim 4. Thus for the same reasons as presented in claim 4, claim 16 when considered in combination with claim 15 and therefore 12, is directed to an abstract idea without significantly more and is not eligible.
Claim 17 is dependent on claim 12, and therefore inherits the same judicial exception as claim 12.
Further claim 17 recites […] wherein each of the one or more threads are operable to generate a command request of the plurality of command request which recites the same limitations as claim 3 and therefore amounts to insignificant extra solution activity which is well understood routine and conventional, as argued in claim 3.
Additional elements of wherein the one or more processors individually comprise one or more cores and one or more threads per the one or more cores are mere instructions to apply and mere instructions to implement in a field of use or technological environment which are well understood routine and conventional and not an integration into a practical application. Therefore the additional elements of claim 17 when considered individually or in combination do not amount to significantly more than the recited judicial exceptions and therefore is ineligible.
Claim 18 is dependent on claim 12, and therefore inherits the same judicial exception as claim 12.
Further claim 18 recites […] directs the first command address to be stored in a first container and […] directs a second command address to be stored in a second container which recites the same limitations as claim 3 and therefore amounts to insignificant extra solution activity which is well understood routine and conventional, as argued in claim 7.
Additional elements of wherein a first thread of the one or more processors and a second thread of the one or more processors are mere instructions to apply and mere instructions to implement in a field of use or technological environment which are well understood routine and conventional and not an integration into a practical application. Therefore the additional elements of claim 18 when considered individually or in combination do not amount to significantly more than the recited judicial exceptions and therefore is ineligible.
Claim 19 is dependent on claim 12, and therefore inherits the same judicial exception as claim 12.
Further claim 19 recites the same limitations as claim 10. Thus for the same reasons as presented in claim 10, claim 19 when considered in combination with claim 12 is directed to an abstract idea without significantly more and is not eligible.
Claim 20 is dependent on claim 12, and therefore inherits the same judicial exception as claim 12.
Further claim 20 recites
wherein transmitting the transformed data to the host device comprises outputting the transform data into one or more output buffers accessible by the host device.
Per Step 2A and 2B
Regarding the additional element (i), the limitation recited amounts to mere data processing steps which is found to be insignificant extra-solution as it is merely storing data after the previous steps influenced by the judicial exception, which is not indicative or integration into a practical application. Further, the additional element (ii) is storing and retrieving information in memory which is well-understood, routine, and conventional activity. See MPEP 2106.05(d). The courts have found adding extra-solution activity and well-understood, routine, and conventional activity is not enough to amount to significantly more than the recited judicial exception. See MPEP 2106.05(a, g)
Accordingly the additional elements amount to mere insignificant extra-solution activity, which when considered individually or in combination are not indicative of integration into a practical application, nor do they amount to significantly more than the recited judicial exceptions. Thus claim 20 is not eligible.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3, 4, 12, 15, 17, 18, and 20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Bachmutsky et al (U.S. Pub. No. 20190317802), referred herein as Bachmutsky.
Regarding claim 1, Bachmutsky teaches A method, comprising: ([0088] FIG. 8A depicts an example process for use by an application to request a workflow execution by a work scheduler.)
obtaining a plurality of command requests, each comprising a command address of a plurality of command addresses; ([0088] At 804, the application can form a combined or universal work descriptor to refer to a sequence of work to be performed. At 806, the application can provide the combined or universal work descriptor(e.g. command request) to a work scheduler to offload management of performance of the sequence of work.; [0049] and Figure 3 In this example, work scheduler 300 is linked to various applications App1 to AppN (e.g. a plurality of applications are instantiating work requests); [0089] At 850, the work scheduler receive a combined work descriptor that references at least one work unit in a sequence of work units. (e.g. obtains a command request); [0090] At 852, the work scheduler can load a descriptor from memory. The combined work descriptor can include a pointer (i.e., a pointer is a variable that contains a memory location or “address” of the work unit, according to Microsoft Computer Dictionary 5e, page 410) to the first work unit or descriptor in memory. The work scheduler can retrieve the first work unit or descriptor.)
performing a load balancing operation to select a first container of a plurality of containers to store a first command address; storing the first command address in the first container;([0052] Egress queues 308 (i.e., multiple “containers” including a “first container”) can be used to buffer (i.e., “Store”) instructions or workloads and scheduling execution by a selected application or accelerator specified by a work request or CWD. In some examples, an application or accelerator can have dedicated ingress and egress queues.; [0053] In other examples, hierarchical scheduler 304 provides quality of service support for placing work requests from ingress queues into a position in an egress queue (i.e., storing a first “command address” into a selected queue) to prioritize or de-prioritize performance of the work request over other work requests. Work scheduler 300 can load balance across multiple applications and/or accelerators for a given processing stage. For instance, if 100 Fast Fourier transform (FFT) operations need to be completed, and two FFT accelerators are available (e.g., assignable execution elements within an accelerator), then the 100 FFT operations can be distributed among the two FFT accelerators (i.e., operations are stored in selected egress queues to balance load across the multiple accelerators).)
transmitting the first command address from the first container to a data transform accelerator; ([0093] At 858, the work scheduler provides the work unit at its egress queue for consumption and processing by the accelerator; [0130] Example 4 includes any example, wherein the work scheduler is to push work requests from the egress queue to a target accelerator.)
and obtaining transformed data from the data transform accelerator. ([0096] At 864, an indication is given to the issuer (e.g., application) of the combined work descriptor that the workflow has completed. Processed data stored in memory can be made available to the issuer of the combined work descriptor.(e.g., processed data is obtained from the data transform accelerator in memory))
Regarding claim 3, Bachmutsky teaches The method of claim 1, wherein the plurality of command requests are generated by one or more software applications, and wherein each software application comprises one or more threads, each thread operable to generate a command request of the plurality of command requests. ([0061] For example, software executed by a core (e.g. software application containing one thread) can create a universal work descriptor (Type-1), array of descriptors (Type-2), or chain of descriptors (Type-3). Upon enqueue of a QE to the work scheduler, work scheduler can manage the performance of the CWD…)
Regarding claim 4, Bachmutsky teaches The method of claim 1, wherein the first command address points to a first command and first input data ([0069] For example, a work descriptor 502 (e.g. the work descriptor that was retrieved from the pointer in of the combined work descriptor) can include one or more of the following fields described below: Table-US-0001 Size Pointer to chain or array of descriptors and their total size. Can point to location and size of global metadata/data in memory; [0070] Global metadata 504 can indicate how accelerators should work on data (e.g. instructions of the data transform operation) Global metadata 504 can include a pointer to… queue entry for work descriptor (a) to be performed by accelerator[0]. [0048] Each queue entry includes two parts, namely, metadata and opaque data. The opaque data portion contains the actual data, or pointers to actual data, to be shared with consumer core,(e.g. input data that is to be transformed) thread, device, and so forth via a dequeue request)
and wherein the data transform accelerator performs a data transform operation to the first input data using the first command.( [0073] In Action (3), accelerator[0] processes data based on information in Global Metadata 504 and Underlying Data 506 and writes resulting processed data to underlying data section 506 in memory. A transform can refer to any mathematical operation, processing, data conversion operations that a particular accelerator performs on a given work item.)
Regarding claim 12, Bachmutsky teaches A system, comprising: a host device, comprising: one or more processors; ([0098] FIG. 9 depicts a system. The system can use embodiments described herein to allocate accelerator traffic to an accelerator memory via an accelerator fabric instead of using a host-to-device fabric. System 900 includes processor 910, which provides processing, operation management, and execution of instructions for system 900. Processor 910 can include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware to provide processing for system 900, or a combination of processors.)
and host software, operated by the one or more processors, to: ([0098] System 900 includes processor 910, which provides processing, operation management, and execution of instructions (e.g. execution host software) for system 900. [0118] Various examples may be implemented using hardware elements, software elements, or a combination of both.)
generate a plurality of command requests, each comprising a plurality of command addresses; ([0061] For example, software executed by a core can create a universal work descriptor (Type-1), array of descriptors (Type-2), or chain of descriptors (Type-3), although embodiments are not limited to these examples. For example, other UWD can be created from any combination of elements in any UWD. [0088] At 804, the application (e.g. processing core) can form a combined or universal work descriptor to refer to a sequence of work to be performed. At 806, the application(e.g. processing core) can provide the combined or universal work descriptor(e.g. command request) to a work scheduler to offload management of performance of the sequence of work.; [0049] and Figure 3 In this example, work scheduler 300 is linked to various applications App1 to AppN (e.g. a plurality of applications or processing cores are instantiating work requests); [0090] The combined work descriptor can include a pointer (i.e., a pointer is a variable that contains a memory location or “address” of the work unit, according to Microsoft Computer Dictionary 5e, page 410) to the first work unit or descriptor in memory. The work scheduler can retrieve the first work unit or descriptor.)
perform a load balancing operation to select a first container of a plurality of containers to store a first command address of the plurality of command addresses; ([0052] Egress queues 308 (i.e., multiple “containers” including a “first container”) can be used to buffer (i.e., “Store”) instructions or workloads and scheduling execution by a selected application or accelerator specified by a work request or CWD. In some examples, an application or accelerator can have dedicated ingress and egress queues.; [0053] In other examples, hierarchical scheduler 304 provides quality of service support for placing work requests from ingress queues into a position in an egress queue (i.e., storing a first “command address” into a selected queue) to prioritize or de-prioritize performance of the work request over other work requests. Work scheduler 300 can load balance across multiple applications and/or accelerators for a given processing stage. For instance, if 100 Fast Fourier transform (FFT) operations need to be completed, and two FFT accelerators are available (e.g., assignable execution elements within an accelerator), then the 100 FFT operations can be distributed among the two FFT accelerators (i.e., operations are stored in selected egress queues to balance load across the multiple accelerators).)
direct the first command address to be stored in the first container; ([0093] At 858, the work scheduler provides the work unit at its egress queue for consumption (e.g. directs the address to the container) and processing by the accelerator)
and transmit the first command address from the first container; ( [0130] Example 4 includes any example, wherein the work scheduler is to push (e.g. transmit) work requests from the egress queue to a target accelerator.)
and at least one data transform accelerator to: ([0147] Example 21 includes a system comprising: …; at least one accelerator )
obtain the first command address transmitted from the first container;( [0130] Example 4 includes any example, wherein the work scheduler is to push work requests from the egress queue to a target accelerator (e.g. accelerator receives the command address). [0097] At 870, an accelerator accesses a memory to retrieve a work unit descriptor based on a request from a work scheduler.)
and transmit transformed data to the host device. ( [0096] At 864, an indication is given to the issuer (e.g. processing core) of the combined work descriptor that the workflow has completed. Processed data stored in memory can be made available to the issuer of the combined work descriptor.(e.g. the transformed data is stored in memory located in the host device))
Regarding claim 15, Bachmutsky teaches wherein the at least one data transform accelerator is further to: obtain a first command associated with the plurality of command requests and first input data using the first command address; ([0097] At 870, an accelerator accesses a memory to retrieve a work unit descriptor based on a request from a work scheduler.(e.g. obtain first command address) ;[0069] For example, a work descriptor 502 (e.g. the work descriptor that was retrieved from the pointer in of the combined work descriptor) can include one or more of the following fields described below: Table-US-0001 Size Pointer to chain or array of descriptors and their total size. Can point to location and size of global metadata/data in memory; [0070] Global metadata 504 can indicate how accelerators should work on data (e.g. instructions of the data transform operation, command) Global metadata 504 can include a pointer to… queue entry for work descriptor (a) to be performed by accelerator[0]. [0048] Each queue entry includes two parts, namely, metadata and opaque data. The opaque data portion contains the actual data, or pointers to actual data, to be shared with consumer core,(e.g. input data that is to be transformed) thread, device, and so forth via a dequeue request; Note: The first command address contains the first command and first input data)
and perform a data transform operation to the first input data using the first command to generate transformed data.( [0073] In Action (3), accelerator[0] processes data based on information in Global Metadata 504 and Underlying Data 506 and writes resulting processed data to underlying data section 506 in memory. A transform can refer to any mathematical operation, processing, data conversion operations that a particular accelerator performs on a given work item.)
Regarding claim 17, Bachmutsky teaches The system of claim 12, wherein the one or more processors individually comprise one or more cores and one or more threads per the one or more cores ([0098] FIG. 9 depicts a system. System 900 includes processor 910... Processor 910 can include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or a combination of processors), and wherein each of the one or more threads are operable to generate a command request of the plurality of command requests. ([0061] For example, software executed by a core (e.g. a core executing software inherently must contain at least one thread) can create a universal work descriptor (e.g. command request) (Type-1), array of descriptors (Type-2), or chain of descriptors (Type-3). Upon enqueue of a QE to the work scheduler, work scheduler can manage the performance of the CWD…)
Regarding claim 18, Bachmutsky teaches The system of claim 17, wherein a first thread of the one or more processors directs the first command address to be stored in a first container ([0020] Various embodiments provide an architecture which enables accelerator chaining such that cores (e.g. multiple cores, thus there is a first core) can construct arrays/lists of accelerator work items which may be submitted once to a work scheduler… The software running on a core sets up all operations in a sequence of work and pre-arranges data transfer(s). (Note: software running on a first core would require a thread of execution, thus there is a first thread) [0061] For example, software executed by a core can create a universal work descriptor (e.g. command request) [0040] In some examples, a universal work descriptor can refer to a first work descriptor that is to be performed by a… accelerator using a pointer for example (e.g. command address). [0088] At 802, the application (e.g. first thread) can determine a sequence of work to be performed on data using one or more accelerators.(e.g. a specific kind of transformation for an accelerator, for example a parser engine, see [0049] and figure 3) At 806, the application (e.g. first thread) can provide the combined or universal work descriptor to a work scheduler to offload management of performance of the sequence of work. [0093] At 858, the work scheduler provides the work unit its egress queue (e.g. store first command address into first “container”) for consumption and processing by the accelerator. [0052] In some examples, an application or accelerator can have dedicated…egress queues. (e.g. the first “container” would be the egress queue for the parser engine, which was directed by the first thread through its request of a specific transformation using a capable accelerator)) a second thread of the one or more processors directs a second command address to be stored in a second container. ( ([0020] Various embodiments provide an architecture which enables accelerator chaining such that cores (e.g. multiple cores, thus there is a second core) can construct arrays/lists of accelerator work items which may be submitted once to a work scheduler… The software running on a core sets up all operations in a sequence of work and pre-arranges data transfer(s). (Note: software running on a second core would require a thread of execution, thus there is a second thread) Similar to the first thread shown above in the paragraph, Bachmutsky discloses, a second thread can create a command address ([0040]) in which it specifies a particular transformation operation to be done by an accelerator of the plurality of accelerators (i.e. encryption and therefore uses a crypto engine) ([0088] and [0049]) The work scheduler would be capable to store that command address at the dedicated egress queue of the accelerator ([0093] and [49]) (e.g. the dedicated queue of the crypto engine, thus a second container) which was directed by the second thread when it requested of a specific transformation using an capable accelerator)
Regarding claim 20, Bachmutsky teaches The system of claim 12, wherein transmitting the transformed data to the host device comprises outputting the transform data into one or more output buffers accessible by the host device. ([0096] At 864, an indication is given to the issuer (e.g. core) of the combined work descriptor that the workflow has completed. Processed data stored in memory(e.g. output buffer) can be made available to the issuer of the combined work descriptor.(e.g. the transformed data is stored in memory located in the host device))
Note: examiner is interpreting “output buffer” to be any data storage medium that can hold data from the accelerator and be accessed to obtain data by host device.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Bachmutsky in view of Gohain et al (U.S. Pub. No. US 20260140827 A1), referred herein as Gohain.
Regarding claim 2, Bachmutsky teaches The method of claim 1. Bachmutsky does not teach further comprising in response to obtaining the transformed data, removing the first command address from the first container.
However Gohain teaches
further comprising in response to obtaining the transformed data, removing the first command address from the first container. ([0059] The memory system controller 215 may execute received commands (e.g. command address) according to an order (e.g., according to the order of the command queue 260). A command may be removed from the buffer queue (e.g. removing address from a container) 265 if the processing of the command has been completed (e.g. transformed data obtained). If a command is removed from the buffer queue 265, the address previously storing the data associated with that command may be available to store data associated with a new command.)
Bachmutsky and Gohain are analogous to the claimed invention as they are both pertinent to the inventive concept of processing of commands from a host device within a secondary processor. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine Gohain’s teachings of queuing commands in a container and executing a command such that after completion of the command, the command is removed from the container, with a reasonable expectation of success, where a scheduler queuing command addresses into a container and pushing the command address to an accelerator to perform some transformation, as in Bachmutsky, could then finish transforming data and delete the address from the queue, as in Gohain. A person having ordinary skill in the art would have been motivated to make the combination to ensure the command is not lost in the case of an interrupt.
Claims 5 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Bachmutsky in view of Unger et al (U.S. Pub. No. US 20220060320 A1), referred herein as Unger.
Regarding claim 5, Bachmutsky teaches The method of claim 4. Bachmutsky does not teach wherein the first input data comprises source data, metadata, and additional data, the additional data comprising one or more of an initialization vector for encryption or decryption, method authentication code, and authentication data for encryption or decryption.
However Unger teaches
wherein the first input data comprises source data, metadata, and additional data, the additional data comprising one or more of an initialization vector for encryption or decryption, method authentication code, and authentication data for encryption or decryption. ([0029] Referring to FIG. 2, a system 110 receives 210 an encrypted packet (e.g., from server 120). The encrypted packet may include data (e.g. source data) and/or header information, such as metadata associated with the data (e.g., a destination address and port or error detection/correction information (e.g. authentication data for decryption)))
Bachmutsky and Unger are analogous to the claimed invention as they are pertinent to encrypting data sent from a host to a processor. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine Unger’s teachings of data sent, by a service, to be encrypted containing source data, metadata, and additional data, with a reasonable expectation of success, where application(s) requesting encryption by sending a command address that points to some first input data to be used by the accelerator as in Bachmutsky, could contain source data, metadata, and additional data as in Unger. A person who has ordinary skill in the art would’ve been motivated to make this combination to ensure downstream accelerators have access to necessary information for encryption or decryption.
Claim 16 recites substantially the same limitations as claim 5, applied to the system of claim 12. As such claim 16 is rejected as being unpatentable over Bachmutsky in view of Unger for the same reasons presented with respect to claim 5.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Bachmutsky in view of Wang et al (U.S. Pub. No. US 20250199890 A1), referred herein as Wang.
Regarding claim 6, Bachmutsky teaches The method of claim 1, wherein plurality of containers… store the plurality of command addresses [0052] Egress queues 308 (i.e., multiple “containers” ) can be used to buffer (i.e., “Store”) instructions or workloads and scheduling execution by a selected application or accelerator specified by a work request or CWD (e.g. address); [0053] In other examples, hierarchical scheduler 304 provides quality of service support for placing work requests (e.g. plurality of addresses) from ingress queues into a position in an egress queue (i.e., storing a first “command address” into a selected queue of multiple queues) to prioritize or de-prioritize performance of the work request over other work requests.
Bachmutsky does not teach containers are command pointer rings
However Wang teaches
containers are command pointer rings ( ([0036] These job descriptors are passed through the communication channel(s) (e.g. containers) either by the shared ring buffer in memory (e.g., as shown in LLC 210) for an accelerator to read (e.g. using queue rings to offload instructions from a sender to a receiver) [0038] Referring to FIGS. 3A and 3B…First, software (e.g., via a processor core) sends a request 302 by writing the job descriptor into the sending agent's (304) internal registers (labeled as descriptor registers 306). The sending agent 304 then uses weakly ordered stores to store the descriptor into the shared ring buffer 346 in memory 318. (e.g. The sender is sending the descriptor to a shared ring buffer))
Bachmutsky and Wang are analogous to the claimed invention because they both are pertinent to processing commands between a host and an accelerator. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine Wang’s teaching of using descriptor queue rings to as an interconnect between a host and accelerator, with a reasonable expectation of success, with Bachmutsky’s teaching of load balancing command addresses from hosts through queues to accelerators, such that those queues are rings as taught in Wang. A person having ordinary skill in the art would have been motivated to make this combination to exposing less low-level hardware specifics to software, while unifying interface and reducing programming effort.(Wang [0023])
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Bachmutsky in view of Tardif (U.S. Pub. No. US 20240394104 A1), referred herein as Tardif.
Regarding claim 7, Bachmutsky teaches The method of claim 1, wherein a first software application stores the first command address in the first container ([0088] FIG. 8A depicts an example process for use by an application to request a workflow execution by a work scheduler. At 802, the application can determine a sequence of work to be performed on data using one or more accelerators.(e.g. first application requests specific kind of transformation for an accelerator) At 806, the application can provide the combined or universal work descriptor to a work scheduler to offload management of performance of the sequence of work. [0093] At 858, the work scheduler provides the work unit its egress queue (e.g. store first command address into first “container”) for consumption and processing by the accelerator.)
Bachmutsky does not teach a second software application stores a second command address in a second container.
However Tardif teaches
a second software application ([0066] This method relates to operating a hardware accelerator configured to process commands submitted by client applications (e.g. multiple software application thus a second application) directly to the hardware accelerator… Any of the client applications 102, 104, or 106 may submit the command for execution of the workload directly (e.g., via path 174 of FIG. 1) to any of the hardware accelerators (e.g., accelerator 1 170, accelerator 2 180, or accelerator M 190 of FIG. 1). stores a second command address in a second container. ([0066] Step 710 may include queueing commands for execution of workloads in a first set of command queues(e.g. storing a second application in a container). [0034] Command queues may also be configured such that there are no command queues that are shared among different types of accelerators.(e.g. a second client application submitting a command request for a different accelerator than the first client application will be store in a second “container”))
Bachmutsky and Tardif are analogous to the claimed invention as they are pertinent to the inventive concept of efficiently processing command requests from applications to accelerators. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine Tardifs teachings of a second application to generate a command request such that the request indicates a specific accelerator and therefore the request is stored in its dedicated work queue, with a reasonable expectation of success, where a system containing one software application storing a command address in a dedicated container of an accelerator, as in Bachmutsky, would contain a second software to store its request in a second container as in Tardif. A person having ordinary skill in the art would have been motivated to make this combination to preserve quality of service for client applications using hardware accelerators (Tardif [0002])
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Jutzi (U.S. Pub. No. 20230376344 A1), referred herein as Jutzi.
Bachmutsky teaches The method of claim 1. Bachmutsky does not teach wherein the load balancing is performed to scale a number of the plurality of command addresses transmitted to the data transform accelerator up to a bandwidth limit associated with the data transform accelerator.
However Jutzi (US 20230376344 A1) teaches
wherein the load balancing is performed to scale a number of the plurality of command addresses transmitted to the data transform accelerator up to a bandwidth limit associated with the data transform accelerator. ([0095] and Fig. 9, Workloads require resources (e.g., processor bandwidth, memory bandwidth, etc.) to implement. The example resource determination circuitry 814 evaluates the ability and/or availability of the resources of the client/edge computing device 704 (e.g., with respect to the amount of resources needed to execute one or more workloads) to determine whether the client/edge computing device 704 is able and/or capable of executing the one or more workloads(i.e. workloads are only distributed up to a bandwidth limit of the edge device). [0097] and [0098] disclose further instructions such that after the resource determination circuitry confirms the capability of the edge device to perform the workload, the workload is then routed to the computing device and is executed)
Bachmutsky and Jutzi are analogous art to the claimed invention as they are both pertinent to the distributing workloads from clients to processors. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine Jutzi’s teachings of distributing workloads based on the edge devices bandwidth such that the if there is not enough bandwidth a workload is not distributed to a device, with a reasonable expectation of success, where a system load balancing command addresses to containers corresponding to an accelerator as in Bachmutsky, could ensure that an accelerator queue would only place addresses into the queue such that the workload stress would not exceed the accelerators bandwidth, as in Jutzi. A person having ordinary skill in the art would have been motivated to make this combination to ensure processors are not being overloaded and prohibit bottlenecks.
Claims 9 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Bachmutsky in view of Fujimoto (U.S. Pub. No. US 20250181401 A1), referred herein as Fujimoto.
Bachmutsky further teaches The method of claim 1, wherein the load balancing is performed according to a class of service ([0133] Example 7 includes any example, wherein the scheduler is to: assign a work request from an ingress queue to an egress queue based on quality of service (QoS) associated with the assigned work request.(e.g. acts as a class of service label and identifies how a work request should be treated))
Bachmutsky does not teach, and the load balancing uses at least one of a round-robin method, a queue depth method, or a CPU core ring method.
However Fujimoto teaches
and the load balancing uses at least one of a round-robin method, a queue depth method, or a CPU core ring method. ([0141] Task scheduler 120 distributes (e.g. load balances) tasks according to the availabilities of the task queues of the request-related processing parts 130. At this time, round robin may be used, or the tasks may be distributed in the ascending order of the number of remaining tasks of the request-related processing parts 130.)
Bachmutsky and Fuji moto are analogous to the claimed invention because they are pertinent to host devices offloading tasks to a secondary processor. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine Fujimoto’s teachings of load balancing tasks to queues using a round robin algorithm, with a reasonable expectation of success, where a load balancing operation that considers a tasks class of service where distributing tasks to containers as in Bachmutsky, could also do so in a round robin algorithm as in Fujimoto. A person having ordinary skill in the art would have been motivated to make this combination to improve overall operation time and operation efficiency (Fujimoto [0003]).
Claim 14 recites substantially the same limitations as claim 9, applied to the system of claim 12. As such claim 14 is rejected as being unpatentable over Bachmutsky in view of Fujimoto for the same reasons presented with respect to claim 9.
Claims 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Bachmutsky in view of Sharique (U.S. Pub. No. US 20200319941 A1), referred herein as Sharique.
Bachmutsky teaches The method of claim 1.
Bachmutsky does not teach wherein the first container is locked for mutual exclusion prior to storing the first command address in the first container, and the first container is unlocked after storing the first command address in the first container.
However Sharique teaches
wherein the first container is locked for mutual exclusion prior to storing the first command address in the first container ([0037] At operation 604, the producer thread can obtain a lock on the work queue (e.g. container). As explained above, the lock ensures that only one thread can access the work queue; [0038] At operation 606, the producer thread can enqueue the work item onto the work queue.), and the first container is unlocked after storing the first command address in the first container.( [0039] At operation 608, the producer thread can generate a work event to signal the activated consumer thread that a work item has been enqueued on the work queue. [0040] At operation 610, the producer thread can release the lock on the work queue, allowing another thread (e.g., a producer thread or a consumer thread) to gain access to the work queue(e.g. the container is unlocked))
Bachmutsky and Sharique are analogous to the claimed invention as they are both pertinent to the communication of commands between two processors. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine Sharique’s teachings of locking a work queue between a producer and consumer when a producer is enqueuing a task and unlocking the queue when the producer finishes the enqueuing instruction, with a reasonable expectation of success, where a system that is offloading commands from a core to queues between the accelerators as in Bachmutsky’s could lock the queue during the storing and unlock when the storing is finish, as taught in Sharique. A person having ordinary skill in the art would have been motivated to make this combination to ensure thread safety and consistency between processors.
Claim 19 recites substantially the same limitations as claim 10, applied to the system of claim 12. As such claim 19 is rejected as being unpatentable over Bachmutsky in view of Sharique for the same reasons presented with respect to claim 10.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Bachmutsky in view of Muthiah (U.S. Pub. No. US 20240086106 A1), referred herein as Muthiah.
Bachmutsky teaches The method of claim 1… such that a first set of command addresses stored in the first set of containers are transmitted to the first data transform accelerator ;( [0130] Example 4 includes any example, wherein the work scheduler is to push work requests(e.g. plurality of command addresses) from the egress queue to a target accelerator.); [0052] Egress queues 308 (i.e., multiple “containers” ) can be used to buffer (i.e., “Store”) instructions or workloads() and scheduling execution by a selected application or accelerator specified by a work request or CWD. In some examples, an application or accelerator can have dedicated ingress and egress queues;(e.g. dedicated egress queues only transmit work between the specified accelerator))
However Bachmutsky does not teach wherein a first set of containers of the plurality of containers is associated with a first data transform accelerator, and are not transmitted to a second data transform accelerator.
However Muthiah teaches
wherein a first set of containers of the plurality of containers is associated with a first data transform accelerator, and are not transmitted to a second data transform accelerator. ([0045] At least one queue (e.g. at least one can be a plurality, thus a set) is configured to queue one or more tasks associated with an accelerator of the one or more accelerators (e.g. the set of queues are dedicated to only one accelerator))
Bachmutsky and Muthiah are analogous art to the claimed invention because they both are pertinent to the inventive concept of using containers to handle a plurality of commands for accelerators. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the sending of command addresses to accelerators of Bachmutsky to include assigning a specific set of containers to a specific accelerator of Muthiah (which would implicitly mean that commands from the first containers would not be sent to the second accelerator) in order to support different bandwidth requirements of different accelerators.(Muthiah [0003])
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Bachmutsky in view of He (U.S. Pub. No. 20180176448), referred herein as He.
Bachmutsky teaches The system of claim 12. Bachmutsky does not teach wherein in response to transmitting the transformed data to the host device the at least one data transform accelerator, the at least one data transform accelerator further to consume the first command address from the first container.
However He teaches
wherein in response to transmitting the transformed data to the host device, the at least one data transform accelerator further to consume the first command address from the first container. ([0059] After the one of the user commands in first queue 103 is processed (e.g. data has been transformed and obtained by the host), processor 104 once again determines if first queue 103 is empty. If first queue 103 is still not empty, processor 104 continues to process the next command in first queue 103.(e.g. the first command has been consumed by the processor) The above process (S501-S503) repeats until first queue 103 turns empty.)
Bachmutsky and He are analogous to the claimed invention as they are both pertinent to the inventive concept of processing of commands from a host device within a secondary processor. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine Bachmutsky’s teaching of a system where an accelerator pulls a work request from a queue (container), transforms data from the command, and transmits the transformed data to the host device, with a reasonable expectation of success, could then pull a subsequent command from the command queue after processing the first command as taught in He. A person having ordinary skill in the art would be motivated to make this combination in order to ensure mitigate the tradeoff between delay time and throughput of a multi-device system (He [0006]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Song et al (U.S. Pub. No. 20240241768) teaches use of priority-based scheduling of tasks. See [0051].
Beracha et al (U.S. Pub. No. 20250039109) teaches the use of load balancing with respect to a queue depth method. See [0078]-[0080].
Dall et al (U.S. Pub. No. 20250284498) teaches the use of accelerator pipelines for processing of data with different executing configuration . See [0063].
Liu et al (U.S. Patent No. 20210089317) teaches the use of queue depth and priority scheduling to schedule tasks across accelerators that have different priority requirements. See [0039]
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/Kayla E Conrad/Examiner, Art Unit 2194 /KEVIN L YOUNG/Supervisory Patent Examiner, Art Unit 2194
