DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 08/28/2024 and 08/06/2025 in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
DISPLAY DEVICE COMPRISING COVERING INORGANIC LAYER
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 and 10-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshida (U.S. PG Pub No US2020/0083256A1).
Regarding claim 1, Yoshida teaches a display device [see fig. 4, 0089] having a plurality of pixels (comprising individual transistors 113-115 and corresponding 118s) fig. 3 [0072] arranged in a matrix (see fig. 2 layout) along a first (horizontal) direction and a second (shown as vertical in fig. 3) direction intersecting the first direction (horizontal), each of the plurality of pixels (comprising 113-115) comprising:
a transistor (comprising 113-115) fig. 4 [0079-0080] including an oxide semiconductor layer (113) fig. 4 [0099] (such as InGaZnO/IGZO [0099]), a gate wiring (115/103G2) fig. 4 [0079-0080, 0106] extending in the first (horizontal) direction opposite (facing opposite) the oxide semiconductor layer (113), and a gate insulating layer (114) fig. 4 [0080] (vertically) between the oxide semiconductor layer (113) and the gate wiring (115/103G2);
a first conductive layer (117A) fig. 4 [0086, 0090] (formed of connective/conductive metal [0098]) provided on (supported by) at least one first insulating layer (112) fig. 4 [0079] (at least partially) above the transistor (comprising 113-115) and in (direct) contact with the oxide semiconductor layer (113);
a second insulating layer (116B) fig. 4 [0101] provided on (supported by) the first conductive layer (117A);
a first inorganic layer (116A) fig. 4 [0101] (such as silicon oxide [0101]) provided on (supported by) the second insulating layer (116B) and having openings (100CH1-3) fig. 4 [0089-0090] therein; and
a second inorganic layer (119) fig. 4 [0100] (such as silicon nitride [0101]) provided on (supported by) the first inorganic layer (116A) and in (thermal) contact with the second insulating layer (116B) in (through) the opening (119 thermally connected to 116B [0100-0101] through conductive 117/118 electrode material [0090, 0102] in opening 110CH3),
wherein a coverage of the first inorganic layer (116A) covering the first insulating layer (112) is 85% or more (100%) of an area (area of portion A1) of the pixel (comprising 118) (100% / entirety of cross-sectional area of A1, as defined in annotated fig. 4 below, covered by 116A).
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Annotated fig. 4 of Yoshida
Regarding claim 2, Yoshida teaches the display device [see fig. 4, 0089] of claim 1. Yoshida also teaches wherein the first inorganic layer (116A) fig. 4 [0101] has (hosts) a second transparent conductive layer (118) fig. 4 [0102] (formed of transparent conductive oxide (TCO) such as ITO [0102]) and a first inorganic insulating layer (116A) fig. 4 [0101] (116A) (inorganic material such as silicon oxide [0101]) on (supported by) the second transparent conductive layer (118), the second transparent conductive layer (118) is (directly) connected to the first conductive layer (117A) fig. 4 [0086, 0090], and the opening (100CH3) fig. 4 [0086] is provided in the first inorganic insulating layer (116A).
Regarding claim 3, Yoshida teaches the display device [see fig. 4, 0089] of claim 2. Yoshida also teaches wherein the second inorganic layer (119) fig. 4 [0100] (such as silicon nitride [0101]) includes (hosts) a third transparent conductive layer (120) fig. 4 [0102] (formed of transparent conductive oxide (TCO) such as ITO [0102]), and the third transparent conductive layer (120) is in (thermal) contact with the second insulating layer (116B) fig. 4 [0101] in (through) the opening (120 and 119 both thermally connected to 116B [0100-0101] through conductive 117/118 electrode material [0090, 0102] in opening 110CH3) and has a slit pattern (indentation of 120 in 100CH3 boundaries) in a region overlapping the second transparent conductive layer (118) fig. 4 [0102].
Regarding claim 4, Yoshida teaches the display device [see fig. 4, 0089] of claim 2. Yoshida also teaches wherein the second inorganic layer (119) fig. 4 [0100] (such as silicon nitride [0101]) includes a second inorganic insulating layer (119 formed of SiN/silicon nitride [0101]), and the second inorganic layer (119) is in (thermal) contact with the second insulating layer (116B) fig. 4 [0101] in (through) the opening (120 and 119 both thermally connected to 116B [0100-0101] through conductive 117/118 electrode material [0090, 0102] in opening 110CH3).
Regarding claim 5, Yoshida teaches the display device [see fig. 4, 0089] of claim 4. Yoshida also teaches wherein the second inorganic layer (119) fig. 4 [0100] includes (hosts) a fourth transparent conductive layer (120) fig. 4 [0102] (formed of transparent conductive oxide (TCO) such as ITO [0102]) provided on (supported by) the second inorganic insulating layer (119) [0101], and the fourth transparent conductive layer (120) has a slit pattern (indentation of 120 in 100CH3 boundaries) in a region overlapping the second transparent conductive layer (118) fig. 4 [0102].
Regarding claim 6, Yoshida teaches the display device [see fig. 4, 0089] of claim 2. Yoshida also teaches wherein the second inorganic layer (119) fig. 4 [0100] includes (hosts) a metal layer (120) fig. 4 [0102] (formed of metal-oxide / metal-comprising oxide such as ITO [0102]), and the metal layer (120) is in (thermal) contact with the second insulating layer (116B) fig. 4 [0101] in (through) the opening (120 and 119 both thermally connected to 116B [0100-0101] through conductive 117/118 electrode material [0090, 0102] in opening 110CH3).
Regarding claim 7, Yoshida teaches the display device [see fig. 4, 0089] of claim 1. Yoshida also teaches wherein the first inorganic layer (116A) fig. 4 [0101] includes (hosts) a first inorganic insulating layer (116A) fig. 4 [0101] (116A) (inorganic material such as silicon oxide [0101]) and a second transparent conductive layer (118) fig. 4 [0102] (formed of transparent conductive oxide (TCO) such as ITO [0102]) provided on (supported by) the first inorganic insulating layer (116A), the second transparent conductive layer (118) is (directly) connected to the first conductive layer (117A) fig. 4 [0086, 0090] via a contact hole (100CH3) fig. 4 [0086] in the first inorganic insulating layer (116B), and the opening (open space of 100CH3) fig. 4 [0086] is arranged in the first inorganic insulating layer (116B).
Regarding claim 8, Yoshida teaches the display device [see fig. 4, 0089] of claim 7. Yoshida also teaches wherein the second inorganic layer (119) fig. 4 [0100] (such as silicon nitride [0101]) includes a second inorganic insulating layer (119 formed of SiN/silicon nitride [0101]), and the second inorganic layer (119) is in (thermal) contact with the second insulating layer (116B) fig. 4 [0101] in (through) the opening (120 and 119 both thermally connected to 116B [0100-0101] through conductive 117/118 electrode material [0090, 0102] in opening 110CH3).
Regarding claim 10, Yoshida teaches the display device [see fig. 4, 0089] of claim 1. Yoshida also teaches further comprising:
a first wiring (101) fig. 2 [0071] (wiring lines) provided on the first insulating layer (112) fig. 4 [0079] and in contact with the oxide semiconductor layer (113) fig. 4 [0099] (such as InGaZnO/IGZO [0099]), wherein the first wiring (101) is provided (extending) along the second direction (vertical direction in fig. 2 view).
Regarding claim 11, Yoshida teaches the display device [see fig. 4, 0089] of claim 1. Yoshida also teaches wherein the opening (100CH3) fig. 4 [0086] is provided in a region overlapping the oxide semiconductor layer (113) fig. 4 [0099].
Regarding claim 12, Yoshida teaches the display device [see fig. 4, 0089] of claim 1. Yoshida also teaches wherein the opening (100CH3) is located in the oxide semiconductor layer (113) fig. 4 [0099] in a region overlapping a region where the gate wiring (115/103G2) fig. 4 [0079-0080, 0106] overlaps in the oxide semiconductor layer (113) fig. 4 [0099].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshida (U.S. PG Pub No US2020/0083256A1), as applied in claim 1 above, in view of Kim (U.S. PG Pub No US2018/0166525A1).
Regarding claim 9, Yoshida teaches the display device [see fig. 4, 0089] of claim 1. Yoshida also teaches:
a first wiring (120) fig. 4 [0102] (acting as a connective wire) provided (horizontally) between the transistor (comprising 113-115) fig. 4 [0079-0080] and the (right portion of) first conductive layer (117A) fig. 4 [0086, 0090] and in (thermal) contact with the oxide semiconductor layer (113) fig. 4 [0099] (such as InGaZnO/IGZO [0099]).
However, Yoshida does not explicitly disclose wherein the first conductive layer (117A) is translucent (117A) (material of connection electrode explicitly disclosed).
Kim teaches a display device [see title, fig. 4] wherein the first conductive layer (211) fig. 9 [0090-0091] is translucent (comprises translucent electrode film [0091]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the display device of Yoshida such that connection electrode explicitly comprises a translucent layer [0090-0091] in order to ensure both favorable conductivity and optical transmission properties in the connective electrode of the display device [0090-0091], as taught by Kim.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshida (U.S. PG Pub No US2020/0083256A1), as applied in claim 1 above, in view of Watakabe (U.S. PG Pub No US2020/0251505A1).
Regarding claim 14, Yoshida teaches the display device [see fig. 4, 0089] of claim 1. However, Yoshida does not explicitly disclose further comprising:
an aluminum oxide layer between the gate insulating layer (114) fig. 4 [0080] and the oxide semiconductor layer (113) fig. 4 [0099].
Watakabe teaches a display device [see title, see fig. 4, 0081] further comprising:
an aluminum oxide layer (31) fig. 4 [0081-0082] between the gate insulating layer (32) fig. 4 [0081-0082] (acting as a gate insulating layer between gate and channel) and the oxide semiconductor layer (13) fig. 4 [0081-0082].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the display device of Yoshida such that the gate insulating material comprises an additional aluminum oxide layer [0081-0082] on the channel [0082] in order to carefully maintain the amount of oxygen in the oxide semiconductor film [0082], as taught by Watakabe.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form are considered relevant to the present disclosure because they all feature display devices with contact openings and a plurality of insulating layers covering each other.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 08/30/2026
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