Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket Number: OTI-033811 US ORD
Filling Date: 08/28/24
Priority Date: 09/01/2023
Inventor: Tsukamoto et al
Examiner: Bilkis Jahan
DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shimizu et al (US 2015/0357276 A1).
Regarding claim 1, Shimizu discloses a stacked wiring substrate (Fig. 1), comprising: a first wiring substrate 11 (Para. 23); and a second wiring substrate 12 (Para. 23) mounted on the first wiring substrate 11, wherein the first wiring substrate 11 includes a first wiring layer 23 (Para. 27), a first insulating layer 20 (Para. 25) covering the first wiring layer 23, a second wiring layer 32 (Para. 28) stacked on an upper surface of the first insulating layer 20 and electrically connected to the first wiring layer 23, a second insulating layer 33 (Para. 31) stacked on the upper surface of the first insulating layer 20 and covering the second wiring layer 32, and a first electrode pad 36 (Para. 28) stacked on an upper surface of the second insulating layer 33 and electrically connected to the second wiring layer 32, the second wiring substrate 12 includes a wiring structure having a wiring density that is higher than that of the first wiring substrate 11, and a second electrode pad 50 (Para. 36) connected to the first electrode pad 36, and a thickness of the second insulating layer 33 is less than a thickness of the first insulating layer 20 (Fig. 1).
Regarding claim 2, Shimizu discloses the stacked wiring substrate according to claim 1, wherein the second insulating layer 33 includes a first through hole 32, 34 extending through the second insulating layer 33 in a thickness-wise direction and exposing part of an upper surface of the second wiring layer 32, and the first electrode pad 36 is formed integrally with first via wiring 34 that fills the first through hole (Fig. 1).
Regarding claim 4, stacked wiring substrate according to claim 1, wherein a thickness of the second via wiring 32 is greater than a thickness of the first wiring layer 23, and a thickness of the first via wiring 34 is equal to or less than a thickness of the second wiring layer 32.
Regarding claim 11, Shimizu discloses the semiconductor device, comprising: the stacked wiring substrate according to claim 1; and a semiconductor chip 81 (Fig. 4, Para. 79) mounted on the second wiring substrate 12.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Shimizu et al (US 2015/0357276 A1).
Regarding claim 3, Shimizu discloses the stacked wiring substrate according to claim 2, wherein the first insulating layer 20 includes a second through hole 21 extending through the first insulating layer 20 in the thickness-wise direction and exposing part of an upper surface of the first wiring layer 23, the second wiring layer is 32 formed integrally with second via wiring 21 that fills the second through hole 21.
Shimizu does not explicitly disclose first via wiring has a size that is smaller than that of the second via wiring in plan view.
However, Shimizu discloses first via wiring 23 and second via wiring 32. Therefore, it would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to obtain first via wiring has a size that is smaller than that of the second via wiring in plan view for intended purposes.
the applicants have not established the criticality (see next paragraph below) of the size.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed size or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 10, Shimizu does not explicitly disclose the stacked wiring substrate according to claim 1, wherein the first electrode pad has a size that is smaller than that of the second electrode pad in plan view.
However, Shimizu discloses the width in the section of the first electrode pad 36 has a size that is smaller than that of the second electrode pad 50 (Para. 36).
It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to obtain the first electrode pad has a size that is smaller than that of the second electrode pad in plan view for intended purposes.
the applicants have not established the criticality (see next paragraph below) of the width.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed width or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Allowable Subject Matter
Claims 5-8 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BILKIS JAHAN whose telephone number is (571)270-5022. The examiner can normally be reached Monday-Friday, 8:00 am-5 Pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon T Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817
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