Prosecution Insights
Last updated: October 04, 2026
Application No. 18/817,630

DISPLAY PANEL, MANUFACTURING METHOD OF DISPLAY PANEL, AND DISPLAY DEVICE

Non-Final OA §103
Filed
Aug 28, 2024
Priority
Jul 26, 2023 — CN 202310938917.5 +1 more
Examiner
ARMAND, MARC ANTHONY
Art Unit
Tech Center
Assignee
Visionox Technology Inc.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
901 granted / 1080 resolved
+23.4% vs TC avg
Minimal +4% lift
Without
With
+4.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
33 currently pending
Career history
1097
Total Applications
across all art units

Statute-Specific Performance

§101
3.7%
-36.3% vs TC avg
§103
58.1%
+18.1% vs TC avg
§102
22.0%
-18.0% vs TC avg
§112
8.4%
-31.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1080 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claims 1-20 are objected to because of the following informalities: the claims pages contain line numbers that should be deleted. Appropriate correction is required. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-3,8,9,12,20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al., (Wang) US 2016/0268361. Regarding claim 1, Wang shows and discloses in FIG. 1-4, a display panel, comprising: a substrate (1)[0038]; an array circuit layer located on the substrate (1) and comprising a plurality of drive transistors (30); a pixel defining layer (11)[0038] and a plurality of sub-pixel units [0008, 0041], wherein the pixel defining layer (11)[0038] and the plurality of sub-pixel units [0008, 0041] are located on a side of the array circuit layer facing away from the substrate (1), and each of the plurality of sub-pixel units [0008, 0041] comprises a first electrode (10a)[0038]; and a first capacitor comprising a first pole plate (9a)[0038] and a second pole plate (9b)[0038], wherein the first pole plate (9a) is disposed on a same layer as the first electrode (10a), the pixel defining layer (11) covers the first pole plate (9a), the second pole plate (9b) is located on a side of the pixel defining layer (11) facing away from the substrate (1), an orthographic projection of the first pole plate (9a) on the substrate (1) at least partially overlaps with an orthographic projection of the second pole plate (9b) on the substrate (1), and the first pole plate (9a) is connected to a gate (2)[0038] of a drive transistor of the plurality of drive transistors (30). Wang discloses the claimed invention except for plurality of drive transistors. It would have been obvious to one having ordinary skill in the art at the time of the invention was made to have a plurality of drive transistors, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. 2144.04. Regarding claim 2, Wang shows and discloses in FIG. 1-4, a display panel wherein the sub-pixel unit further comprises a second electrode (10b), the second electrode (10b) is located on a side of the pixel defining layer (11) facing away from the substrate, and a material of the second pole plate (9b) is different from a material of the second electrode (10b). As for the different material, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to have a different material, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use. In re Leshin, 125 USPQ 416. MPEP 2144.07. Regarding claim 3, Wang shows and discloses in FIG. 1-4, a display panel wherein the second pole plate (9b) is disposed on a different layer from the second electrode (10b). Regarding claim 8, Wang shows and discloses in FIG. 1-4, a display panel wherein the pixel defining layer (11) comprises a plurality of pixel defining portions (11, could be duplicated) and an opening region formed by enclosing the plurality of pixel defining portions, and the first electrode (10a) is exposed outside the opening region; and a pixel defining portion (11) of the plurality of pixel defining portions covers the first pole plate (9a), the second pole plate (9b) is located on a side of the pixel defining portion facing away from the substrate (1), and the pixel defining portion (11) spaces the first pole plate (9a) apart from the second pole plate (9b), wherein the first pole plate (9a) is insulated from the second pole plate (9b). Regarding claim 9, Wang shows and discloses in FIG. 1-4, a display panel wherein the pixel defining portion (11) comprises at least one of a silicon oxide layer or a silicon nitride layer [0052]. Regarding claim 10, Wang shows and discloses in FIG. 1-4, a display panel wherein a thickness of the pixel defining portion (11) in a direction perpendicular to the substrate. As for the particular range of the pixel from 100 nm to 1000 nm, the Applicant did not show criticality of the particular range of the pixel from 100 nm to 1000 nm. To establish unexpected results over a claimed range or optimum value, applicants should compare a sufficient number of tests both inside and outside the claimed range to show the criticality of the claimed range. In re Hill, 284 F.2d 955, 128 USPQ 197 (CCPA 1960). Regarding claim 12, Wang shows and discloses in FIG. 1-4, a display panel wherein the first pole plate (9a) is insulated from the first electrode (10a), and part of the first pole plate (9a) is located between adjacent first electrodes (10a); the first pole plate (9a) is disposed around the first electrode (10a); and the second pole plate (9b) is disposed around the opening region of the pixel defining layer (11), and an overlapping region between the orthographic projection of the first pole plate (9a) on the substrate and the orthographic projection of the second pole plate (9b) on the substrate surrounds the opening region. Regarding claim 20, Wang shows and discloses in FIG. 1-4, a display device, comprising a display panel, wherein the display panel comprises: a substrate (1); an array circuit layer located on the substrate and comprising a plurality of drive transistors (30); a pixel defining layer (11) and a plurality of sub-pixel units [0008, 0041], wherein the pixel defining layer (11) and the plurality of sub-pixel units [0008, 0041] are located on a side of the array circuit layer facing away from the substrate (1), and each of the plurality of sub-pixel units comprises a first electrode (10a); and a first capacitor comprising a first pole plate (9a) and a second pole plate (9b), wherein the first pole plate (9a) is disposed on a same layer as the first electrode (10a), the pixel defining layer covers the first pole plate (9a), the second pole plate (9b) is located on a side of the pixel defining layer facing away from the substrate (1), an orthographic projection of the first pole plate (9a) on the substrate at least partially overlaps with an orthographic projection of the second pole plate (9b) on the substrate, and the first pole plate (9a) is connected to a gate (2) of a drive transistor of the plurality of drive transistors (30). Wang discloses the claimed invention except for plurality of drive transistors. It would have been obvious to one having ordinary skill in the art at the time of the invention was made to have a plurality of drive transistors, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. 2144.04. Allowable Subject Matter Claims 4-7,11,13,14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 15-19 are allowed. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARC-ANTHONY ARMAND whose telephone number is (571)272-5178. The examiner can normally be reached 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. MARC - ANTHONY ARMAND Primary Examiner Art Unit 2813 /MARC-ANTHONY ARMAND/ Primary Examiner, Art Unit 2813
Read full office action

Prosecution Timeline

Aug 28, 2024
Application Filed
Aug 24, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751156
DISPLAY PANEL AND DISPLAY APPARATUS
3y 5m to grant Granted Sep 29, 2026
Patent 12751162
DISPLAY DEVICE
2y 11m to grant Granted Sep 29, 2026
Patent 12751336
ISOLATOR
3y 0m to grant Granted Sep 29, 2026
Patent 12745437
NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
3y 4m to grant Granted Sep 22, 2026
Patent 12740137
INTEGRATED CIRCUIT WITH FINFET WITH SHORTER AND NARROWER FIN UNDER GATE ONLY
3y 1m to grant Granted Sep 15, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
88%
With Interview (+4.2%)
2y 5m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1080 resolved cases by this examiner. Grant probability derived from career allowance rate.

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