DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on August 28, 2024 and IDS filed on September 24, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDSs are considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-8 and 17-19 are rejected are rejected under 35 U.S.C. 103 as being unpatentable over Sung et al. US 2022/0093647 in view of Xie et al. US 2023/0095140.
Regarding claim 1, Sung teaches a forksheet field-effect transistor (FET) device (e.g., 620, Fig. 6, [55]-[58]; also see the devices of Figs. 7-8 for additional details) comprising:
a first FET (e.g., first FET including 608, Fig. 6) comprising a first conductive gate material (e.g., material of 608, Fig. 6, [74]);
a second FET (e.g., second FET including 610, Fig. 6) that is adjacent the first FET; and
a conductive wall (e.g., 622, Fig. 6, [62]) that separates the first FET from the second FET and that comprises a second conductive gate material (e.g., material of 622, [62]) that is different from the first conductive gate material.
Sung does not explicitly teach a second FET that comprises the first conductive gate material.
Sung, however, recognizes that the first FET and second FET pertain to forksheet transistors, and 608 of the first FET includes an NMOS gate stack with an n-type material and 610 of the second FET includes a PMOS gate stack with a p-type material (e.g., [55], [56]).
Xie teaches forksheet transistors may be realized between one NFET and one PFET, two NFETs, two PFETs, and the like (e.g., [50], [2]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Sung to include two NFETs or two PFETs as suggested by Xie because it has been well known in the art that one NFET and one PFET, two NFETs, two PFETs, and the like are alternative embodiments commonly used for forming forksheet transistors as suggested by Xie, and selecting among them would have been obvious to the skilled artisan. MPEP §2143. In this case, Sung in view of Xie thus teaches a second FET that comprises the first conductive gate material.
Regarding claim 6, Sung in view of Xie teaches the forksheet FET device of Claim 1, wherein the conductive wall is at a cell boundary of the forksheet FET device (e.g., Sung; cell boundary between the first and second FETs/cells (discussed above) at which 622 is disposed, Fig. 6).
Regarding claim 7, Sung in view of Xie teaches the forksheet FET device of Claim 1 as discussed above.
Sung in view of Xie does not explicitly teach wherein the conductive wall is configured to control a threshold voltage of the forksheet FET device.
Sung in view of Xie, however, recognizes that because the conductive wall 622 (e.g., Sung, Fig. 6) is placed at the same location (i.e., at the cell boundary called CB1 and CB2) as disclosed in Fig. 2C of Applicant’s original disclosure (e.g., [45]), and the configuration of 622 to be biased via the contact 626 (e.g., Sung, [57], [58]) is the same as disclosed in Fig. 2B of Applicant’s original disclosure (e.g., [35]), the conductive wall 622 may function as a gate electrode. Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the conductive wall of Sung in view of Xie may perform the claimed function, i.e., controlling a threshold voltage of the forksheet FET device for example.
Regarding claim 8, Sung in view of Xie teaches the forksheet FET device of Claim 1, wherein the first FET and the second FET are both p-type metal-oxide-semiconductor (PMOS) transistors or are both n-type metal-oxide-semiconductor (NMOS) transistors (see the discussion regarding claim 1 above).
Regarding claim 17, Sung teaches a forksheet field-effect transistor (FET) device (e.g., 620, Fig. 6, [55]-[58]; also see the devices of Figs. 7-8 for additional details) comprising:
a first FET (e.g., first FET including 608, Fig. 6) comprising a first conductive gate material (e.g., material of 608, Fig. 6, [74]);
a second FET (e.g., second FET including 610, Fig. 6) that is adjacent the first FET; and
a second conductive gate material (e.g., material of 622, Fig. 6, [62]) that is between the first FET and the second FET and that is different from the first conductive gate material.
Sung does not explicitly teach a second FET that comprises the first conductive gate material; wherein the first FET and the second FET each comprise the same conductivity type transistor.
Sung, however, recognizes that the first FET and second FET pertain to forksheet transistors, and 608 of the first FET includes an NMOS gate stack with an n-type material and 610 of the second FET includes a PMOS gate stack with a p-type material (e.g., [55], [56]).
Xie teaches forksheet transistors may be realized between one NFET and one PFET, two NFETs, two PFETs, and the like (e.g., [50], [2]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Sung to include two NFETs or two PFETs as suggested by Xie because it has been well known in the art that one NFET and one PFET, two NFETs, two PFETs, and the like are alternative embodiments commonly used for forming forksheet transistors as suggested by Xie, and selecting among them would have been obvious to the skilled artisan. MPEP §2143. In this case, Sung in view of Xie thus teaches a second FET that comprises the first conductive gate material; wherein the first FET and the second FET each comprise the same conductivity type transistor.
Regarding claim 18, Sung in view of Xie teaches the forksheet FET device of Claim 17, wherein the first conductive gate material is part of a first gate electrode (e.g., Sung, first gate structure including 608, Fig. 6, [74]), and wherein the second conductive gate material is part of a second gate electrode (e.g., Sung, second gate structure including 618 and 622, Fig. 6, [73]) that is a high-k metal gate (HKMG) electrode.
Regarding claim 19, Sung teaches a forksheet field-effect transistor (FET) device (e.g., 620, Fig. 6, [55]-[58]; also see the devices of Figs. 7-8 for additional details) comprising:
a first FET (e.g., first FET including 608, Fig. 6);
a second FET (e.g., second FET including 610, Fig. 6) that is side by side with the first FET; and
a gate material (e.g., material of 622, Fig. 6, [62]) that separates the first FET from the second FET.
Sung does not explicitly teach that (i) a gate material is configured to control a threshold voltage of the forksheet FET device; and (ii) a second FET has the same conductivity type as the first FET.
Regarding (i), Sung, however, recognizes that because the conductive wall 622 (e.g., Fig. 6) is placed at the same location (i.e., at the cell boundary called CB1 and CB2) as disclosed in Fig. 2C of Applicant’s original disclosure (e.g., [45]), and the configuration of 622 to be biased via the contact 626 (e.g., [57], [58]) is the same as disclosed in Fig. 2B of Applicant’s original disclosure (e.g., [35]), the conductive wall 622 may function as a gate electrode. Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the conductive wall of Sung may perform the claimed function, i.e., controlling a threshold voltage of the forksheet FET device for example.
Regarding (ii), Sung, however, recognizes that the first FET and second FET pertain to forksheet transistors, and 608 of the first FET includes an NMOS gate stack with an n-type material and 610 of the second FET includes a PMOS gate stack with a p-type material (e.g., [55], [56]). Xie teaches forksheet transistors may be realized between one NFET and one PFET, two NFETs, two PFETs, and the like (e.g., [50], [2]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Sung to include two NFETs or two PFETs as suggested by Xie because it has been well known in the art that one NFET and one PFET, two NFETs, two PFETs, and the like are alternative embodiments commonly used for forming forksheet transistors as suggested by Xie, and selecting among them would have been obvious to the skilled artisan. MPEP §2143. In this case, Sung in view of Xie thus teaches a second FET has the same conductivity type as the first FET.
Claims 9 and 10 are rejected are rejected under 35 U.S.C. 103 as being unpatentable over Sung in view of Xie as applied to claim 1 above, and further in view of Chen et al. US 2024/0153874.
Regarding claim 9, Sung in view of Xie teaches the forksheet FET device of Claim 1, further comprising: a first gate structure (e.g., Sung, first gate structure including 608, Fig. 6, [74]) that includes the first conductive gate material; and a second gate contact (e.g., Sung, 626, Fig. 6) that is on the conductive wall and is configured to bias a second gate structure that includes the conductive wall (e.g., Sung, Fig. 6).
Sung in view of Xie does not explicitly teach a first gate contact that is on the first conductive gate material and is configured to bias a first gate structure.
Chen teaches a gate contact (e.g., 114, Fig. 1) that is on the conductive gate material (e.g., material of 108, Fig. 1) and is configured to bias a gate structure (e.g., 108, Fig. 1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the first gate structure of Sung in view of Xie may include a first gate contact that is on the first conductive gate material and is configured to bias the first gate structure as suggested by Chen for the purpose of properly operating the forksheet FET device for example.
Regarding claim 10, Sung in view of Xie and Chen teaches the forksheet FET device of Claim 9, wherein the second gate contact (e.g., Sung, 626, Fig. 6) is in contact with the conductive wall (e.g., 622, Fig. 6).
Claims 1, 7 and 19 are rejected are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. US 2023/0207563 in view of Xie et al. US 2023/0095140.
Regarding claim 1, Cheng teaches a forksheet field-effect transistor (FET) device (e.g., 200, Fig. 2, [42]-[45]) comprising:
a first FET (e.g., first FET including 110, Fig. 2, [29]) comprising a first conductive gate material (e.g., material of 110, Fig. 2, [39], [41]);
a second FET (e.g., second FET including 112, Fig. 2, [29]) that is adjacent the first FET; and
a conductive wall (e.g., 216, Fig. 6) that separates the first FET from the second FET and that comprises a second conductive gate material (e.g., material of 216; work function of the gate pillar 216 is intermediate between a work function of the first gate stack and a work function of the second gate stack, [55]) that is different from the first conductive gate material.
Cheng does not explicitly teach a second FET that comprises the first conductive gate material.
Cheng, however, recognizes that the first FET and second FET pertain to forksheet transistors, and 110 of the first FET includes a PMOS gate stack with a p-type material and 112 of the second FET includes an NMOS gate stack with an n-type material (e.g., [29], [39], [41]).
Xie teaches forksheet transistors may be realized between one NFET and one PFET, two NFETs, two PFETs, and the like (e.g., [50], [2]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Cheng to include two NFETs or two PFETs as suggested by Xie because it has been well known in the art that one NFET and one PFET, two NFETs, two PFETs, and the like are alternative embodiments commonly used for forming forksheet transistors as suggested by Xie, and selecting among them would have been obvious to the skilled artisan. MPEP §2143. In this case, Cheng in view of Xie thus teaches a second FET that comprises the first conductive gate material.
Regarding claim 7, Cheng in view of Xie teaches the forksheet FET device of Claim 1, wherein the conductive wall is configured to control a threshold voltage of the forksheet FET device (e.g., Cheng, [43]).
Regarding claim 19, Cheng teaches a forksheet field-effect transistor (FET) device (e.g., 200, Fig. 2, [42]-[45]) comprising:
a first FET (e.g., first FET including 110, Fig. 2, [29]);
a second FET (e.g., second FET including 112, Fig. 2, [29]) that is side by side with the first FET; and
a gate material (e.g., material of 216, Fig. 2, [55]) that separates the first FET from the second FET and that is configured to control a threshold voltage of the forksheet FET device (e.g., [43]).
Cheng does not explicitly teach that a second FET has the same conductivity type as the first FET.
Cheng, however, recognizes that the first FET and second FET pertain to forksheet transistors, and 110 of the first FET includes a PMOS gate stack with a p-type material and 112 of the second FET includes an NMOS gate stack with an n-type material (e.g., [29], [39], [41]).
Xie teaches forksheet transistors may be realized between one NFET and one PFET, two NFETs, two PFETs, and the like (e.g., [50], [2]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Cheng to include two NFETs or two PFETs as suggested by Xie because it has been well known in the art that one NFET and one PFET, two NFETs, two PFETs, and the like are alternative embodiments commonly used for forming forksheet transistors as suggested by Xie, and selecting among them would have been obvious to the skilled artisan. MPEP §2143. In this case, Cheng in view of Xie thus teaches a second FET has the same conductivity type as the first FET.
Allowable Subject Matter
Claims 2-5 and 11-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The art made of record and not applied to the rejection is considered pertinent to applicant's disclosure. It is cited primarily to show inventions relevant to the examination of the instant invention. For example, Weekx et al. US 11,164,942 and Neumann et al. US 2023/0126135 relate to a forksheet field-effect transistor (FET) device including a wall separating two FETs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bo Bin Jang whose telephone number is (571) 270-0271. The examiner can normally be reached on M-F from 9:00 AM to 6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BO B JANG/Primary Examiner, Art Unit 2818 August 21, 2026
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