DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to an Application filed on 08/28/2024.
Currently, claims 1-12 are examined as below.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statements (IDS) filed on 08/28/2024 and 03/14/2025. The IDS have been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
(Marked-Up Version) Semiconductor Device Having a Field Effect Transistor Stacking on a Capacitor
(Clean Version) Semiconductor Device Having a Field Effect Transistor Stacking on a Capacitor
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 6 and 11-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 is indefinite, because the limitation “the at least part of the non-array region groove” in line 12 is not mentioned before. Only “at least a part of the groove” is recited in the base claim 1. There is insufficient antecedent basis.
Claim 6 is indefinite, because the limitation “the recessed groove” in line 2 is not mentioned before. There is insufficient antecedent basis.
Claim 11 is indefinite, because the limitation “the recessed groove” in line 2 is not mentioned before. There is insufficient antecedent basis.
Claim 12 is indefinite, because:
(1) The limitation “the depth” in line 3 is not mentioned before. There is insufficient antecedent basis.
(2) The limitation “the at least part of the non-array region groove” is not mentioned before. There is insufficient antecedent basis.
(3) The limitation “the thickness direction” is not mentioned before. There is insufficient antecedent basis.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claims 1, 3-5 and 7-10 are allowed.
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Regarding independent claim 1, US 2021/0225847 A1 to Wada et al. (“Wada”) in Figs. 1 and 4-5 teaches a semiconductor device (Fig. 1, ¶ 25 & ¶ 29, semiconductor memory device including capacitor 30 and field effect transistor 51 in Figs. 4-5) comprising:
a channel 501 (Figs. 4-5, ¶ 38, channel layer 501 including an oxide semiconductor) comprising an oxide semiconductor layer 501 (¶ 38, channel layer 501 including an oxide semiconductor) in a through hole (Fig. 5, space accommodating the layer 501);
a first electrode 42 (Figs. 1, 4-5, ¶ 38, oxide conductive layer 42) in a first side (Fig. 5, upper side) of the through hole, the first electrode 42 being connected to a first side (Fig. 5, upper side) of the channel 501 (Figs. 4-5);
a second electrode 31, 41 (Figs. 1, 4-5, ¶ 32, ¶ 36, a collective of cell electrode 31 and oxide conductive layer 41) in a second side (Fig. 5, lower side) of the through hole, the second electrode 31, 41 being connected to a second side (Fig. 5, lower side) of the channel 501 (Figs. 4-5); and
an insulating layer 32 (Fig. 5, ¶ 32, insulating film 32) having a groove (Fig. 5, space within the insulating layer 32 accommodating the electrode 31) in which at least a part of the second electrode 31, 41 is accommodated;
the groove extending in a thickness direction (Fig. 5), and
the second electrode 31, 41 comprising a cell electrode 31 (Figs. 4-5, ¶ 32) and a conductive film 41 (Figs. 4-5, ¶ 36, oxide conductive layer 41) stacked on the cell electrode 31, the cell electrode 31 being in contact with at least an inner bottom surface of the groove (Fig. 5).
Wada does not explicitly disclose the cell electrode is a metal film.
US 6,172,389 B1 to Sakoh recognizes a need for obtaining a large capacity per unit area for the capacitor element (col. 3, ln. 8-18). Sakoh satisfies the need by using a refractive metal for the cell electrode (col. 3, ln. 8-18).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to use the refractive metal taught by Sakoh for the cell electrode taught by Wada, so as to obtain a large capacity per unit area for the capacitor element (Sakoh: col. 3, ln. 8-18).
However, the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 1, the insulating layer comprising a first insulating film and a second insulating film, the first insulating film being closer to the channel than the second insulating film, and at least a part of the groove having a depth where at least a part of the groove penetrates through the first insulating film in the thickness direction and reaches the second insulating film.
Therefore, independent claim 1 is allowed.
Claims 3-5 are allowed, because they depend from the allowed claim 1.
Regarding independent claim 7, Wada in Figs. 1 and 4-5 teaches a semiconductor device (Fig. 1, ¶ 25 & ¶ 29, semiconductor memory device including capacitor 30 and field effect transistor 51 in Figs. 4-5) comprising:
a channel 501 (Figs. 4-5, ¶ 38, channel layer 501 including an oxide semiconductor) comprising an oxide semiconductor layer 501 (¶ 38, channel layer 501 including an oxide semiconductor) in a through hole (Fig. 5, space accommodating the layer 501);
a first electrode 42 (Figs. 1, 4-5, ¶ 38, oxide conductive layer 42) in a first side (Fig. 5, upper side) of the through hole, the first electrode 41 being connected to a first side (Fig. 5, upper side) of the channel 501 (Figs. 4-5);
a second electrode 31, 41 (Figs. 1, 4-5, ¶ 32, ¶ 36, a collective of cell electrode 31 and oxide conductive layer 41) in a second side (Fig. 5, lower side) of the through hole, the second electrode 31, 41 being connected to a second side (Fig. 5, lower side) of the channel 501 (Figs. 4-5); and
an insulating layer 32 (Fig. 5, ¶ 32, insulating film 32) having a groove (Fig. 5, space within the insulating layer 32 accommodating the electrode 31) in which at least a part of the second electrode 31, 41 is accommodated,
the second electrode 31, 41 comprising a cell electrode 31 (Figs. 4-5, ¶ 32) and a conductive film 41 (Figs. 4-5, ¶ 36, oxide conductive layer 41) stacked on the cell electrode 31, the cell electrode 31 being in contact with at least an inner bottom surface of the groove (Fig. 5).
Wada does not explicitly disclose the cell electrode is a metal film comprising at least one of: a conductive oxide film containing one of titanium oxide, titanium oxynitride, ruthenium oxide, and molybdenum oxide; and a stack of a titanium layer and a titanium nitride layer.
US 2020/0381557 A1 to Hattori et al. (“Hattori”) recognizes a need for an oxide semiconductor transistor having high heat resistance and small fluctuation in characteristics after heat treatment (¶ 4). Hattori satisfies the need by providing a cell electrode 71 (Fig. 11, ¶ 115) comprising a conductive oxide film 71 containing titanium oxide (¶ 115), which is the material for the metal film as required by claim 7.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to use the titanium oxide taught by Hattori for the metal film/cell electrode taught by Wada, so as to provide an oxide semiconductor transistor having high heat resistance and small fluctuation in characteristics after heat treatment (Hattori: ¶ 4).
However, the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 7, the insulating layer comprising a first insulating film and a second insulating film, the first insulating film being closer to the channel than the second insulating film.
Therefore, independent claim 7 is allowed.
Claims 8-10 are allowed, because they depend from the allowed claim 7.
Claims 2, 6 and 11-12 are rejected.
Claims 2, 6 and 11-12 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 2 and 6 would be allowable, because they depend from the allowed claim 1.
Claims 11-12 would be allowable, because they depend from the allowed claim 7.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 9,698,272 B1 to Ikeda et al. relates to a transistor including a first electrode, a second electrode, a current path between the first and second electrodes, the current path including an oxide semiconductor layer, a control terminal, an insulating layer between the control terminal and the oxide semiconductor layer, a first oxide layer between the first electrode and the oxide semiconductor layer, and a second oxide layer between the second electrode and the oxide semiconductor layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKKA LIU whose telephone number is (571)272-2568. The examiner can normally be reached on 9AM-5AM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.L./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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