DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file (IT102023000017769 Italian Republic 08/29/2023).
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 08/28/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Drawings
The drawings submitted on 08/28/2024. These drawings are review and accepted by the examiner.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract of the disclosure is objected to because it uses the phrase “comprising” in page 1, lines 1, 3, 5, which is implied. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 14, 15 are recited the limitation "the enable signals" in claims 1, 14, 15. There is insufficient antecedent basis for this limitation in the claim. Claims 2-13, 16-20 depend from claims 1, 14, 15 and therefore contain the same matter.
Allowable Subject Matter
Claims 1-20 would be allowable if corrected to overcome the objections/rejections set forth above.
The following is an examiner’s statement of reasons for allowance:
The prior art made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitations. Matthews et al (US 5,737,275) discloses a boost circuit, a word drive circuit and a row decoder, and includes a first P-channel MOS transistor, a second P-channel MOS transistor, a first N-channel MOS transistor, and a second N-channel MOS transistor; Katoh et al (US 2010/0110767 A1) discloses a voltage exceeds a first voltage and is switched to a low-resistance state when the voltage exceeds a second voltage, a controller, a voltage restricting active element which is connected in series with the resistance variable element; Chung et al (US 8,068,381 B2) discloses a row decoder which decodes and outputs an input address signal; a plurality of word-line voltage control logic units which output a basic voltage signal or a reinforcement voltage signal having a higher voltage level than the basic voltage signal according to whether or not word lines involve a cell having an access time failure. However, Matthews/Katoh/Chung, taken individually or in combination, do not teach the claimed invention having the following limitations, in combination with the remaining claimed limitations:
Per claim 1, there is no teaching, suggestion, or motivation for combination in the prior art to a demultiplexer configured to provide for each word-line a respective enable signal, and to assert one of the enable signals as a second function of the address signal, wherein the demultiplexer is supplied by the second supply voltage, wherein each enable signal is connected to either the second supply voltage or the ground, wherein the second supply voltage is smaller than the first supply voltage, and wherein the row decoder comprises for each word-line: a pull-up connected between the respective word-line and the first supply voltage; a first n-channel field-effect transistor (FET), wherein a source terminal of the first n-channel FET is connected to the ground, and a gate terminal of the first n-channel FET is connected to a first signal; a second n-channel FET, wherein a drain terminal of the second n-channel FET is connected to the respective word-line, a source terminal of the second n-channel FET is connected to a drain terminal of the first n-channel FET, and a gate terminal of the second n-channel FET is connected to the second voltage; a first p-channel FET, wherein a drain terminal of the first p-channel FET is connected to the second voltage, a source terminal of the first p-channel FET is connected to the respective word-line, and a gate terminal of the first p-channel FET is connected to a second signal; a bias circuit configured to set a drain voltage at the drain terminal of the first n-channel FET to the second voltage when the first n-channel FET and the second n-channel FET are opened; a first delay circuit configured to: detect changes in the enable signal; in response to detecting a change from an asserted logic level to a de-asserted logic level of the enable signal, connect the first signal to the ground; and in response to detecting a change from the de-asserted logic level to the asserted logic level of the enable signal, set the first signal after a first delay to a voltage in order to close the first FET; and a second delay circuit configured to: detect the changes in the enable signal; in response to detecting the change from the de-asserted logic level to the asserted logic level of the enable signal, set the second signal to the second voltage; and in response to detecting the change from the asserted logic level to the de-asserted logic level of the enable signal, set the second signal after a second delay to the first voltage, in combination with the other limitations in the claim.
Per claim 14, there is no teaching, suggestion, or motivation for combination in the prior art to a demultiplexer configured to provide for each word-line a respective enable signal, and to assert one of the enable signals as a second function of the address signal, wherein the demultiplexer is supplied by the second supply voltage, wherein each enable signal is connected to either the second supply voltage or the ground, wherein the second supply voltage is smaller than the first supply voltage, and wherein the row decoder comprises for each word-line: a pull-up connected between the respective word-line and the first supply voltage; a first n-channel field-effect transistor (FET), wherein a source terminal of the first n-channel FET is connected to the ground, and a gate terminal of the first n-channel FET is connected to a first signal; a second n-channel FET, wherein a drain terminal of the second n-channel FET is connected to the respective word-line, a source terminal of the second n-channel FET is connected to a drain terminal of the first n-channel FET, and a gate terminal of the second n-channel FET is connected to the second voltage; a first p-channel FET, wherein a drain terminal of the first p-channel FET is connected to the second voltage, a source terminal of the first p-channel FET is connected to the respective word-line, and a gate terminal of the first p-channel FET is connected to a second signal; a bias circuit configured to set a drain voltage at the drain terminal of the first n-channel FET to the second voltage when the first n-channel FET and the second n-channel FET are opened; a first delay circuit configured to: detect changes in the enable signal; in response to detecting a change from an asserted logic level to a de-asserted logic level of the enable signal, connect the first signal to the ground; and in response to detecting a change from the de-asserted logic level to the asserted logic level of the enable signal, set the first signal after a first delay to a voltage in order to close the first FET; and a second delay circuit configured to: detect the changes in the enable signal; in response to detecting the change from the de-asserted logic level to the asserted logic level of the enable signal, set the second signal to the second voltage; and in response to detecting the change from the asserted logic level to the de-asserted logic level of the enable signal, set the second signal after a second delay to the first voltage, in combination with the other limitations in the claim.
Per claim 15, there is no teaching, suggestion, or motivation for combination in the prior art to a demultiplexer configured to provide for each word-line a respective enable signal, and to assert one of the enable signals as a first function of an address signal, the demultiplexer being supplied by the second supply voltage, each enable signal being connected to either the second supply voltage or ground, and the row decoder comprising, for each word-line, a pull-up connected between the respective word-line and the first supply voltage, a first n-channel field-effect transistor (FET), a source terminal of the first n-channel FET being connected to the ground, and a gate terminal of the first n-channel FET is connected to a first signal, a second n-channel FET, a drain terminal of the second n-channel FET being connected to the respective word-line, a source terminal of the second n-channel FET is connected to a drain terminal of the first n-channel FET, and a gate terminal of the second n-channel FET is connected to the second voltage, a first p-channel FET, a drain terminal of the first p-channel FET being connected to the second voltage, a source terminal of the first p-channel FET is connected to the respective word-line, and a gate terminal of the first p-channel FET is connected to a second signal, a bias circuit, a first delay circuit, and a second delay circuit, the method comprising: providing the first supply voltage and the second supply voltage to the non-volatile memory, the second supply voltage being smaller than the first supply voltage; and providing the address signal to the row decoder, in combination with the other limitations in the claim.
Conclusion
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/THA-O H BUI/Primary Examiner, Art Unit 2825 02/12/2026