Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated August 28, 2024, claims 1-19 are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Foreign Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)
(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statements filed August 28, 2024 have been considered.
Claim Objections
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1, it is unclear if the “program-inhibited voltage” is meant to be reduced to the precharge voltage, or if the “verification precharge voltage” is a separate, subsequent voltage level applied after discharging.
The dependent claims, claims 2-9 are rejected because they depend on the indefiniteness of the claims from which they depend.
Claim Rejections- 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 2 is/are rejected, as understood, under 35 U.S.C. 102(a)(1) as being anticipated by Choi [US Patent Application # 20230290412].
With respect to claim 1, Choi discloses a memory device [pars. 0010-0011], comprising: a bit line control circuit configured to apply a verification precharge voltage after a program pulse period ["performing a program verification operation of verifying a program result by precharging the bit lines using a precharge voltage" - involve precharging the bit lines specifically for verification after a program pulse] to a program-inhibited bit line maintaining a program-inhibited voltage ["setting a... program inhibit voltage of a plurality of bit lines" - establish the management of bit lines that should not be programmed.] during the program pulse period; and a row decoder configured to form a channel in a string coupled between the program-inhibited bit line and a source line ["...coupling to a selected word line..." - describe the structure of NAND flash strings connected to a word line], wherein the program-inhibited voltage of the program-inhibited bit line is discharged through the channel to the verification precharge voltage ["wherein a level of the precharge voltage... is decreased when the number of program loops... is greater than a reference number" - describe discharging high inhibit voltages to a specific, lower voltage (the verification voltage) during verification, a method often adjusted based on loop count to mitigate disturb]. It is noted that Choi’s method ("decreasing precharge voltage”) necessitates the device components ("bit line control circuit" and "row decoder”) described in the claimed recitation. Additionally, Choi’s method involves components: 121, 123, 124 and 125 of fig. 2. Further, claimed recitation describes discharging the inhibit voltage to a verification precharge voltage, which is inherently part of the "decreased" precharge operation in Choi’s method described in pars. 0010-0011. The act of "discharging... to the verification precharge voltage" is the action that lowers the bit line voltage from a high "program-inhibited voltage" to the lower "precharge voltage." Therefore, the procedural steps in Choi necessitate the structural and functional limitations in the claimed recitation.
With respect to claim 2, Choi discloses, in pars. 0010-0011, the row decoder is further configured to form the channel [Implied within "setting a program permission voltage and a program inhibit voltage of a plurality of bit lines" (setting channels)] at a memory cell turn-on time after the program pulse period [Corresponds to the transition between "performing a program voltage application operation" and the subsequent "program verification operation"], and the bit line control circuit is further configured to apply the verification precharge voltage ["precharging the bit lines using a precharge voltage" within the "program verification operation"] to the program-inhibited bit line ["setting a... program inhibit voltage of a plurality of bit lines"] at a precharge time after the memory cell turn-on time ["performing a program verification operation... [wherein] the setting, the program voltage application operation, and the program verification operation are repeatedly performed"].
Claim(s) 18 is/are rejected, as understood, under 35 U.S.C. 102(a)(1) as being anticipated by Koo et al. [US Patent # 9,082,487].
With respect to claim 18, Koo et al. disclose a method of performing a program operation with a memory device, the method [figs. 1 and 2] comprising: determining, with a control circuit [170 of fig. 1], a precharge method for a program verification operation [s160] as a first precharge method when a program operation is determined to be completed for a predetermined program state among a plurality of program states [s150 and col. 5, lines 15-35]; and discharging, with a peripheral circuit [150 of fig. 1], a program-inhibited voltage of a program-inhibited bit line to a verification precharge voltage after a program pulse period [“In the step S132, the bit line of the selected memory cell is maintained in the state discharged in the step S120 “ – col. 5, lines 30-40] according to the first precharge method.
Allowable Subject Matter
Claims 10-17 are allowable over the prior art of record.
The following is an Examiner's statement of reasons for the indication of
allowable subject matter: the prior art of records does not show (in addition to the other
elements in the claim) the following:
-with respect to claim 10: the program-inhibited voltage of the program-inhibited bit line is discharged to the verification precharge voltage; and a row decoder configured to apply a verification voltage to a selected word line while the verification precharge voltage is being applied to the program-inhibited bit line.
-with respect to claim 19: The method according to claim 18, further comprising: determining, with the control circuit, the precharge method as a second precharge method when a program operation is determined to be incomplete for the predetermined program state; and discharging, with the peripheral circuit, the program-inhibited voltage of the program-inhibited bit line to a ground voltage after the program pulse period and then precharging the program-inhibited bit line to the verification precharge voltage according to the second precharge method.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 February 11, 2026