Prosecution Insights
Last updated: October 04, 2026
Application No. 18/818,632

SEMICONDUCTOR PACKAGES WITH THERMAL DISSIPATION

Non-Final OA §102§103
Filed
Aug 29, 2024
Priority
Aug 29, 2023 — provisional 63/579,297
Examiner
BRECHT, CHARLES MATTHEW
Art Unit
Tech Center
Assignee
UTAC Headquarters Pte. Ltd.
OA Round
1 (Non-Final)
Grant Probability
Favorable
1-2
OA Rounds

Examiner Intelligence

Grants only 0% of cases
0%
Career Allowance Rate
0 granted / 0 resolved
-60.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
Avg Prosecution
40 currently pending
Career history
26
Total Applications
across all art units
This examiner has no resolved cases yet (career too new); statute-level performance unavailable. The Grant Probability card shows Tech Center averages instead.

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-6, 8-12, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sirinorakul et al. (2022/0028798, hereafter Sirinorakul). Regarding claim 1, Sirinorakul discloses a method for forming a semiconductor package comprising: providing a package substrate (510, Fig. 5d), the package substrate having top and bottom package substrate surfaces, wherein the top surface is configured with a die attach pad (DAP) (512) and package pads (516); attaching a bottom die surface of a die (530a) to the DAP, wherein the die is electrically coupled to the package pads (Fig. 5d); attaching a primary heat dissipator (550, par. 0042) to the package substrate and a top die surface of the die, wherein the primary heat dissipator comprises a planar member (554) disposed over the top die surface, the heat dissipator is configured to dissipate heat from the die (par. 0042); encapsulating the package substrate with an encapsulant (580), the encapsulant covers the package substrate and encases the die and the primary heat dissipator, wherein a top encapsulant surface is coplanar with the top planar member surface (Fig. 5d); and forming a secondary heat dissipator (560) on the top encapsulant surface, wherein the secondary heat dissipator contacts a top planar member surface of the primary heat dissipator to enhance heat dissipation from the die (par. 0111) (Fig. 5d). Regarding claim 2, Sirinorakul discloses a method wherein attaching the primary heat dissipator (550) to the package substrate includes electrically connecting the primary heat dissipator to ground (516 left) (Fig. 5d). Regarding claim 3, Sirinorakul discloses a method wherein the primary heat dissipator (550, Fig. 5d) comprises a pre-formed thermally conductive metallic structure (par. 0034, 0069). Regarding claim 4, Sirinorakul discloses a method wherein attaching the primary heat dissipator comprises a thermal adhesive for attaching the primary heat dissipator to the package substrate and die (par. 0037). Regarding claim 5, Sirinorakul discloses a method wherein the primary heat dissipator (550) comprises a planar member (554) with a leg member (552) extending from a first side of the planar member to the package substrate (510) and a die connector member (570) extending from the planar member to contact the top die surface (Fig. 5d). Regarding claim 6, Sirinorakul discloses a method wherein: the die (530a) comprises die pads (par. 0030, 0064) on the top die surface; wire bonds (540a-540c) connect the die pads to package pads (516); and wherein the planar member (554) of the primary heat dissipator (550) is disposed above the wire bonds to prevent the primary heat dissipator from interfering with the wire bonds (Fig. 5d). Regarding claim 8, Sirinorakul discloses a method wherein: the die (530a) comprises die pads (par. 0030, 0064) on the top die surface; wire bonds (540a-540c) connect the die pads to package pads (516); and wherein the planar member (554) of the primary heat dissipator (550) is disposed above the wire bonds to prevent the primary heat dissipator from interfering with the wire bonds (Fig. 5d). Regarding claim 9, Sirinorakul discloses a method wherein forming the secondary heat dissipator (560, Fig. 5d) comprises sputtering a metallic layer on the top encapsulant surface (par. 0119). Regarding claim 10, Sirinorakul discloses a method further comprises forming a tertiary heat dissipator (590, Fig. 5d) on a top surface of the secondary heat dissipator, wherein the tertiary heat dissipator further enhances heat dissipation of the die (par. 0111). Regarding claim 11, Sirinorakul discloses a method wherein forming the tertiary heat dissipator (590, Fig. 5d) comprises sputtering a metallic layer on the secondary heat dissipator (par. 0076). Regarding claim 12, Sirinorakul discloses a method wherein forming the tertiary heat dissipator (590, Fig. 5d) comprises attaching a heat sink to the secondary heat dissipator (par. 0111). Regarding claim 15, Sirinorakul discloses a semiconductor package comprising: a package substrate (510), the package substrate having top and bottom package substrate surfaces, wherein the top surface is configured with a die attach pad (DAP) (512) and package pads (516); a die (530a) having top bottom die surfaces, wherein the bottom die surface is disposed on the DAP, wherein the die is electrically coupled to the package pads (Fig. 5d); a primary heat dissipator (550) attached to the package substrate and a top die surface of the die, wherein the primary heat dissipator comprises a planar member (554) disposed over the top die surface, the heat dissipator is configured to dissipate heat from the die; an encapsulant (580), the encapsulant covers the package substrate and encases the die and the primary heat dissipator, wherein a top encapsulant surface is coplanar with a top planar member surface; and a secondary heat dissipator (560) disposed on the top encapsulant surface, wherein the secondary heat dissipator contacts the top planar member surface of the primary heat dissipator to enhance heat dissipation from the die (par. 0111) (Fig. 5d). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Sirinorakul. Regarding claim 7, Sirinorakul, discussed above, fails to explicitly disclose a method wherein the primary heat dissipator comprises a planar member with first and second leg members extending from first and second sides of the planar member to the package substrate and a die connector member extending from the planar member to contact. However, in another embodiment, Sirinorakul teaches a method wherein the primary heat dissipator (650) comprises a planar member (650 top) with first and second leg members (650 left/right) extending from first and second sides of the planar member to the package substrate (610) and a die connector member (670) extending from the planar member to contact (Fig. 6b). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Sirinorakul by providing a heat dissipator with a first and second leg extending to the package substrate and die in order to elevate the planar member above the die so as not to contact the bond wires, and to short together the package pads on the other side of the structure. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Sirinorakul in view of Fukui (2015/0221580, hereafter Fukui). Regarding claim 13, Sirinorakul, discussed above, fails to explicitly disclose a method wherein the die comprises a flip-chip die, wherein die contacts are disposed on the bottom die surface, the die contacts are coupled to package pads. However, in another embodiment, Sirinorakul teaches a method wherein the die comprises a flip-chip die, wherein die contacts are disposed on the bottom die surface, the die contacts are coupled to package pads (par. 0031). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Sirinorakul by providing contacts on the die to contact the package in order to provide higher interconnect density, lower parasitic capacitance, and superior electrical/thermal performance. Sirinorakul fails to disclose the planar member of the primary heat dissipator directly contacts the top die surface. However, Fukui teaches the planar member of the primary heat dissipator directly contacts the top die surface (par. 0046). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Sirinorakul with Fukui by providing a heat dissipator in direct contact with the die in order to minimize thermal interface layers and reduce thermal resistance. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Sirinorakul in view of Chiang (5877552, hereafter Chiang). Regarding claim 14, Sirinorakul, discussed above, fails to explicitly disclose a method wherein the die comprises a flip-chip die, wherein die contacts are disposed on the bottom die surface, the die contacts are coupled to package pads. However, in another embodiment Sirinorakul teaches method wherein the die comprises a flip-chip die, wherein die contacts are disposed on the bottom die surface, the die contacts are coupled to package pads (par. 0031). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Sirinorakul by providing contacts on the die to contact the package in order to provide higher interconnect density, lower parasitic capacitance, and superior electrical/thermal performance. Sirinorakul fails to disclose a heat slug is disposed on the top die surface; and the planar member of the primary heat dissipator directly contacts the heat slug surface. However, Chiang teaches a heat slug (120) is disposed on the top die surface (102); and the planar member (120 top) of the primary heat dissipator directly contacts the heat slug surface (Fig. 4A). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Sirinorakul with Chiang by providing a heat slug between the die and dissipator in order to act as a thermal spreader and prevent damage by relieving thermal stress. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M BRECHT whose telephone number is (571)272-9634. The examiner can normally be reached Mon-Fri: 7:30am - 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (572) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.M.B./Examiner, Art Unit 2817 /MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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Prosecution Timeline

Aug 29, 2024
Application Filed
Sep 11, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
Grant Probability
Low
PTA Risk
Based on 0 resolved cases by this examiner. Grant probability derived from career allowance rate.

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