DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 5, 7, 9, 11 and 12 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Wang et al. (US Pat Pub 2020/0043980).
Regarding claim 1, Wang et al. disclose a semiconductor memory device comprising:
a first memory cell comprising a first variable resistor element (figure 4, ref. BC; paragraph [0003,0025]) and a first cell transistor (figure 4, ref. MBT; paragraph [0016]) connected to the first variable resistor element through a first source-drain electrode (figure 4, ref. SNC, S/D; paragraph [0025]);
a substrate (figure 4, ref. S; paragraph [0023]) comprising a first surface (upper surface SA) connected to a second source-drain electrode (figure 4, ref. S/D, Vsl; paragraph [0026]) of the first cell transistor and a second surface opposing the first surface (lower surface SB);
a first bitline (figure 4, ref. BL; paragraph [0019]) connected to the first source-drain electrode of the first cell transistor through the first variable resistor element (as shown); and
a first source line (figure 4, ref. SL; paragraph [0025]) having a first width (inherent), arranged on the second surface of the substrate and connected to the second source-drain electrode (as shown, fig. 4).
Regarding claim 2, Wang et al. also disclose the semiconductor memory device of claim 1, comprising: a first back contact located inside the substrate and extending from the second surface, wherein the first source line is connected to the second source-drain electrode through the first back contact (see figure 4, ref. Vsl the description, paragraph [0077], of the application, indicates that a via is equivalent to a "back contact").
Claims 11 and 12 are also rejected based on grounds for the rejection of claims 1 and 2 above; see further fig. 4 with reference BC.
Regarding claim 3, Wang et al. also disclose the semiconductor memory device of claim 2, comprising:
a first front contact connected to the first source-drain electrode on the first surface of the substrate; and a first metal line stacked on the first front contact, wherein the first bitline is connected to the first source-drain electrode through the first variable resistor element, the first front contact, and the first metal line (see figure 4, ref. S/D, Vsnc).
Regarding claims 4 and 9, Wang et al. also disclose the semiconductor memory device of claim 1, wherein the first variable resistor element comprises: a first magnetic layer, a second magnetic layer, and a tunnel layer disposed between the first magnetic layer and the second magnetic layer, and wherein the first variable resistor element has different resistance values depending on a magnetization direction of the first magnetic layer and a magnetization direction of the second magnetic layer, which are formed depending on current applied through the first bitline (see paragraph [0018]).
Regarding claim 5, Wang et al. also disclose the semiconductor memory device of claim 1, further comprising: a first wordline connected to a first gate electrode of the first cell transistor on the first surface of the substrate (see figure 4, ref. PWL; paragraph [0021]).
Regarding claim 7, Wang et al. also disclose the semiconductor memory device of claim 1, further comprising: a second memory cell disposed adjacent to the first memory cell and comprising a second variable resistor element and a second cell transistor; and a second bitline connected to a third source-drain electrode of the second cell transistor through the second variable resistor element, wherein the second cell transistor is connected to the first source line, disposed on the second surface of the substrate, through the substrate (see figure 4, ref. BC).
Allowable Subject Matter
Claims 19 and 20 are allowed.
Claims 6, 8, 10 and 13 – 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior arts of record fail to teach or reasonably suggest the semiconductor memory device as set forth above, further comprising, in combination, the additional word lines on the second surface of the substrate, a second source line with a different width on the second surface of the substrate, or an additional back contact, as further disclosed at least in claims 6, 8, 10, 13 and 15-19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
See amended claims 1 – 13 from the European counterpart application EP 25150137 submitted 31 December 2025.
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LY D. PHAM
Examiner
Art Unit 2827
/LY D PHAM/Primary Examiner, Art Unit 2827 February 4, 2026