DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, & 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (US 2023/0088828) [Hereinafter Liu].
Regarding claim 1, Liu teaches A semiconductor device comprising:
a substrate [fig. 8, substrate 10, para 19] including a first surface [fig. 8, S2] extending in a first direction and a second direction;
a first transistor [fig. 8, MOSFET MOS1];
a light receiver [fig. 8, light receiving element 40, para 18];
a light emitter [fig. 8, light emitter 60, para 18] provided on the light receiver (fig. 8, 40);
an input terminal [fig. 8, input terminal 80, para 36] provided on the first surface of the substrate (fig. 8, 10);
a first conductor [fig. 8, wire W25, para 63] configured to electrically couple a source electrode [fig. 8, electrode 22a, para 21] of the first transistor (fig. 8, MOS1) and a first electrode [fig. 8, electrode 41, para 31] of the light receiver (fig. 8, 40);
a second conductor [fig. 7, wire W26, para 63] configured to electrically couple a gate electrode [fig. 7, electrode 23a, para 21] of the first transistor (fig. 7, MOS1) and a second electrode [fig. 7, electrode 42, para 31] of the light receiver (fig. 7, 40); and
a third conductor [fig. 8, conductor 85, para 37] configured to couple a third electrode of the light emitter [fig. 8, electrode 61, para 69] and the input terminal (fig. 7, 80),
wherein the light emitter (fig. 8, 60) and the input terminal (fig. 8, 80) are provided at positions overlapping with each other in a third direction [fig. 8, z-direction] intersecting the first direction and the second direction, and
the third conductor (fig. 8, 85) is provided inside the substrate (fig. 8, 10).
Regarding claim 3, Liu teaches The semiconductor device according to claim 1,
wherein a light receiving surface of the light receiver is provided to face a light emitting surface of the light emitter [fig. 8, claim 5].
Regarding claim 11, Liu teaches The semiconductor device according to claim 1, further comprising:
a second transistor [fig. 7, transistor MOS3, para 25] provided so as to be aligned with the first transistor (fig. 7, MOS3) in the second direction (y-direction); and
a fifth conductor [fig. 7, wire W30, para 64] configured to electrically couple a gate electrode [fig. 7, electrode 23c, para 26] of the second transistor (fig. 7, MOS3) and a fourth electrode [fig. 7, electrode 44, para 66] of the light receiver (fig 7, 40),
wherein the first conductor [fig. 8, wire W25, para 63] further electrically couples a source electrode (fig. 7, electrode 22c, para 26) of the second transistor (fig. 7, MOS3) to the source electrode (fig. 7, electrode 22a, para 21] of the first transistor (fig. 7, MOS1) and the first electrode of the light receiver (fig. 7, 41).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Liu as applied to claims 1, 3, & 11 and further in view of itself.
Regarding claim 5, Liu teaches The semiconductor device according to claim 1, further comprising:
a first output terminal (fig. 3, 82a) provided on the first surface (fig. 3, S2) of the substrate (fig. 3, 10); and
a fourth conductor [fig. 3, 87a] configured to electrically couple the first output terminal (fig. 3, 82a) and a drain electrode (fig. 3, 21a) of the first transistor (fig. 3, MOS1),
wherein the fourth conductor (fig. 3, 87a) is provided inside the substrate (fig. 3, 10).
Claim(s) 4, 6, & 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Liu as applied to claims 1, 3, & 11 and further in view of Ito (JP2013214765A).
Regarding claim 4, Liu teaches The semiconductor device according to claim 1,
wherein the substrate (fig. 8, 10) further includes a second surface (fig. 8, S1) extending in the first direction (fig. 8, x-direction) and the second direction (fig. 8, y-direction) and different from the first surface (fig. 8, S2).
Liu fails to explicitly disclose the first conductor and the second conductor are provided inside the substrate and on the second surface.
However Ito teaches the first conductor [fig. 1, conductors 42] and the second conductor [fig. 1, conductors 42, “The end surfaces of the corresponding interlayer conductors 42 and 62 are in pressure contact with the top or bottom surfaces of the electrodes 52*”] are provided inside the substrate [fig. 1, component embedded substrate 1A] and on the second surface.
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the conductors to be inside the substrate layer rather than on the surface to physically and electrically optimize the 3D space by reducing parasitic capacitance and reducing the overall required surface footprint enabling thin devices.
Regarding claim 6, Liu teaches The semiconductor device according to claim 1.
While Liu discloses the first transistor embedded in a sealing resin and also mounted on a resin substrate.
Liu fails to explicitly disclose wherein the first transistor is provided inside the substrate so as to be embedded in the substrate.
Ito teaches wherein the first transistor [fig. 1, component 52, “components 52 and 53 is a chip of an electronic circuit element such as a capacitor, a coil, or a transistor”] is provided inside the substrate [fig. 1, substrate 1A] so as to be embedded in the substrate [fig. 1].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the transistors to be embedded in the substrate as a component built in layer creating an embedded die substrate to reduce distance signals and better heat management in smaller device form factors.
Regarding claim 13, Liu teaches The semiconductor device according to claim 11,
wherein the substrate (fig. 8, 10) further includes
a second surface (fig. 8, S1) extending in the first direction and the second direction and different from the first surface, and
the first conductor [fig. 8, wire W25, para 63], the second conductor [fig. 7, wire W26, para 63], and the fifth conductor [fig. 7, wire W30, para 64] are provided inside the substrate and on the second surface (fig. 7, S2).
While Liu notes the first conductor, the second conductor, and the fifth conductor are provided (embedded) inside a resin layer.
Liu fails to explicitly disclose the first conductor, the second conductor, and the fifth conductor are provided inside the substrate.
However, Ito teaches the first conductor, the second conductor, and the fifth conductor are provided (embedded) inside the substrate [Ito teaches in fig. 1 an embedded built in substrate 1A wherein all conductors coupled to the components 52/53 are inside the substrate 1A].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the conductors to be provided inside the substrate to reduce distance signals and better heat management in smaller device form factors.
Regarding claim 14, Liu/Ito teaches The semiconductor device according to claim 11, further comprising:
a second output terminal [Liu, fig. 3, output terminal 82c, para 50] provided on the first surface (Liu, fig. 3, S2) of the substrate (Liu, fig. 3, 10); and
a sixth conductor [Liu, fig. 3, 87c] configured to electrically couple the second output terminal (Liu, 82c) and a drain electrode [Liu, fig. 3, 21c, para 26] of the second transistor (Liu, fig. 3, MOS3),
wherein the sixth conductor (Liu, fig. 3, 82c) is provided inside the substrate.
Regarding claim 15, Liu/Ito teaches The semiconductor device according to claim 11,
wherein the first transistor [Ito, fig. 1, 53] and the second transistor [Ito, fig. 1, 52, “Each component such as components 52 and 53 is a chip of an electronic circuit element such as a capacitor, a coil, or a transistor”] are provided inside the substrate so as to be embedded in the substrate [Ito, fig. 1, component embedded substrate 1A].
Allowable Subject Matter
Claims 2, 7-10, 12, & 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, Liu teaches The semiconductor device according to claim 1,
wherein the input terminal [fig. 8, 80),
the substrate (fig. 8, 10),
the light emitter, and the
light receiver are sequentially disposed in the third direction.
The prior art of record fails to explicitly disclose the light emitter and the light receiver sequentially disposed in the third direction.
Thereby claim 2 contains allowable subject matter in light of the additional limitations recited therein and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims..
Regarding claim 7, Liu/Ito teaches The semiconductor device according to claim 4.
The prior art of record fails to explicitly disclose wherein the substrate includes an opening recessed in the third direction on the second surface,
the light emitter is provided in the opening of the substrate so as to be aligned with the first transistor in the first direction,
the first electrode of the light receiver is in contact with the first conductor on the second surface of the substrate, and
the second electrode of the light receiver is in contact with the second conductor on the second surface of the substrate.
Thereby claim 7 contains allowable subject matter in light of the additional limitations recited therein and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 8 contains allowable subject matter at least based upon its dependency on claim 7,
Regarding claim 9, Liu/Ito teaches The semiconductor device according to claim 4.
The prior art of record fails to explicitly disclose wherein the first conductor and the second conductor further include a portion extending in the third direction outside the substrate, and
the third electrode of the light emitter is in contact with the third conductor on the second surface of the substrate.
Thereby claim 9 contains allowable subject matter in light of the additional limitations recited therein and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 10 contains allowable subject matter at least based upon its dependency on claim 9.
Regarding claim 12, Liu teaches The semiconductor device according to claim 11.
The prior art of record fails to explicitly disclose in entirety wherein the first conductor has a flat plate shape extending in the first direction and the second direction, and is
provided so as to cover the source electrode of the first transistor and the source electrode of the second transistor.
Thereby claim 12 contains allowable subject matter in light of the additional limitations recited therein and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 16, Liu/Ito teaches The semiconductor device according to claim 13.
The prior art of record fails to explicitly disclose in entirety wherein the substrate includes an opening recessed in the third direction on the second surface,
the light emitter is provided in the opening of the substrate so as to be aligned with the first transistor and the second transistor in the first direction, the first electrode of the light receiver is in contact with the first conductor on the second surface of the substrate, the second electrode of the light receiver is in contact with the second conductor on the second surface of the substrate, and the fourth electrode of the light receiver is in contact with the fifth conductor on the second surface of the substrate.
Thereby claim 16 contains allowable subject matter in light of the additional limitations recited therein and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 17 contains allowable subject matter at least based upon its dependency on claim 16.
Regarding claim 18, Liu/Ito teaches The semiconductor device according to claim 13.
The prior art of record fails to explicitly disclose in entirety wherein the first conductor, the second conductor, and the fifth conductor further include a portion extending in the third direction outside the substrate,
and the third electrode of the light emitter is in contact with the third conductor on the second surface of the substrate.
Thereby claim 18 contains allowable subject matter in light of the additional limitations recited therein and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 19 contains allowable subject matter at least based upon its dependency on claim 18.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FELIX B ANDREWS whose telephone number is (703)756-1074. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm ET.
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/FELIX B ANDREWS/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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