Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated April 16, 2026, claims 1-26 are active in
this application.
Election
John Ward [Reg. No. 40216] made a provisional election without traverse to prosecute the
invention of Group 1 directed to Sense amplifiers or other reading circuitry, claims 1-23, classified in G11C 7/06. Affirmation of this election was made in the response to the restriction requirements.
Claims 24-26 are withdrawn from further consideration by the Examiner, 37
C.F.R. § 1.142(b), as being drawn to a non-elected invention.
Applicant is reminded that upon the cancellation of claims to a non-elected invention, the
inventorship must be amended in compliance with 37 C.F.R. § 1.48(b) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. Any amendment of inventorship must be accompanied by a diligently-filed petition under 37 C.F.R. § 1.48(b) and by the fee required under 37 C.F.R. § 1.17(h).
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Information Disclosure Statement
The information disclosure statements filed September 12, 2024 through November 11, 2025
have been considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 of U.S. Patent No. 12080365 [‘365]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘365
1. (Original) A device, comprising: a plurality of memory cells each respective memory cell in the plurality of memory cells with a respective programming sensitivity different from the respective programming sensitivity of other memory cells in the plurality; and reading circuitry configured to read respective analog information programmed in the respective memory cells and to provide an output based on a combination of the respective analog information read from the respective memory cells.
1. A device, comprising: a multi-deck memory array; a plurality of respective memory cells, each memory cell in the respective memory cells having a programming sensitivity different from programming sensitivities of other memory cells in the respective memory cells, wherein the respective memory cells being on different decks of the multi-deck memory array; and reading circuitry configured to read respective analog information programmed in the respective memory cells and to provide an output based on a combination of the respective analog information read from the respective memory cells, wherein the respective memory cells include a first memory cell and a second memory cell, comprising of different storage material; a first storage element of the first memory cell comprises a first storage material; and a second storage element of the second memory cell comprises a second storage material different from the first storage material.
2. (Original) The device of claim 1, comprising a multi-deck memory array, the respective memory cells being on different decks of the multi-deck memory array.
“…the respective memory cells being on different decks of the multi-deck memory array…” – see claim 1.
3. (Original) The device of claim 2, wherein a first storage element of a first memory cell comprises a first storage material and a second storage element of a second memory cell comprises a second storage material different from the first storage material.
“…a first storage element of the first memory cell comprises a first storage material; and a second storage element of the second memory cell comprises a second storage material different from the first storage material….” – see claim 1.
4. (Original) The device of claim 2, wherein a first storage element of a first memory cell comprises a storage material with first thickness and a second storage element of a second memory cell comprises the storage material with a second thickness that is different from the first thickness.
2. The device of claim 1, a first storage element of the first memory cell comprises a storage material with first thickness; and a second storage element of the second memory cell comprises the storage material with a second thickness that is different from the first thickness.
5. (Original) The device of claim 2, wherein the respective memory cells comprise a first memory cell comprising: a first middle electrode between a first word line and a first digit line, a first selection element between the first word line and the first middle electrode, and a first storage element between the first middle electrode and the first digit line, the first storage element having a first thickness and a first composition, and a second memory cell comprising: a second middle electrode between a second digit line and a second word line, a second selection element between the second digit line and the second middle electrode, and a second storage element between the second middle electrode and the second word line, the second storage element having a second thickness equal to the first thickness and a second composition equal to the first composition.
3. The device of claim 1, wherein the respective memory cells comprise: a first memory cell comprising: a first middle electrode between a first word line and a first digit line; a first selection element between the first word line and the first middle electrode; and a first storage element between the first middle electrode and the first digit line, the first storage element having a first thickness and a first composition; and a second memory cell comprising: a second middle electrode between a second digit line and a second word line; a second selection element between the second digit line and the second middle electrode; and a second storage element between the second middle electrode and the second word line, the second storage element having a second thickness equal to the first thickness and a second composition equal to the first composition.
6. (Original) The device of claim 1, wherein the reading circuit is configured to read respective analog information based at least in part on a respective resistance, a respective conductance or a respective threshold voltage of the respective memory cells.
4. The device of claim 1, wherein the reading circuitry is configured to read respective analog information based at least in part on a respective resistance, a respective conductance or a respective threshold voltage of the respective memory cells.
7. (Original) The device of claim 6, wherein the reading circuit is configured to non-destructively read respective analog information programmed in the respective memory cells.
5. The device of claim 4, wherein the reading circuitry is configured to non-destructively read respective analog information programmed in the respective memory cells.
8. (Original) The device of claim 1, wherein each respective memory cell in the plurality of memory cells is configured to change state at a respective rate different from other respective state change rates of other respective memory cells in response to one or more programming pulses applied to the memory cells during an analog programming operation.
6. The device of claim 1, wherein each respective memory cell in the plurality of memory cells is configured to change state at a respective rate different from other respective state change rates of other respective memory cells in response to one or more programming pulses applied to the memory cells during an analog programming operation.
9. (Original) The device of claim 1, wherein the plurality of memory cells is configured to store a synaptic weight.
7. The device of claim 1, wherein the plurality of memory cells is configured to store a synaptic weight.
As can be seen from the above table, the application’s claim 1 encompass a sub-combination or a broader genus of the device claimed in Patent 365’s claim 1. Patent 365 recites the identical core combination (programming sensitivity, reading circuitry providing an output based on a combination) but adds specific limitations, such as a multi-deck array and specific differing storage materials. Claiming a broader grouping of this exact device (leaving the storage material unspecified) in the application is an obvious variation of the narrower, specific device in Patent 365. Therefore, the patent protections have been granted to the earlier filed patent application.
For similar reasons, claims 2-9 are rejected over claims 1-7 of patent ‘365.
Claims 10-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 6, 8, 9, 12 and 13 of U.S. Patent No. 12080365 [‘365]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘365
10. (Original) A method comprising: accessing a plurality of memory cells each respective memory cell in the plurality of memory cells with a respective programming sensitivity different from the respective programming sensitivity of other cells in the plurality; applying one or more programming pulses to the plurality of memory cells; and storing respective analog information in each respective memory cell based at least in part on the applying the one or more programming pulses.
8. A method comprising: accessing a plurality of memory cells in a multi-deck memory array, each respective memory cell in the plurality of memory cells having a programming sensitivity different from programming sensitivities of other cells in the plurality of memory cells, the respective memory cells being on different decks of the multi-deck memory array; reading, from the each respective memory cell, analog information programmed in the plurality of memory cells; combining the analog information read from the each respective memory cell, wherein the respective memory cells include a first memory cell and a second memory cell, comprising of different storage material; providing an output based on combining the analog information; and a first storage element of the first memory cell comprises a first storage material; and a second storage element of the second memory cell comprises a second storage material different from the first storage material.
11. (Original) The method of claim 10, wherein accessing the plurality of memory cells comprises biasing respective access lines coupled to respective memory cells on different decks of a multi-deck memory array.
9. The method of claim 8 wherein accessing the plurality of memory cells comprises biasing respective access lines coupled to respective memory cells on different decks of a multi-deck memory array.
12. (Original) The method of claim 10, wherein storing respective analog information comprises changing state of each respective memory cell at a respective rate different from other respective state change rates of other respective memory cells in response to applying the one or more programming pulses to the plurality of memory cells.
6. The device of claim 1, wherein each respective memory cell in the plurality of memory cells is configured to change state at a respective rate different from other respective state change rates of other respective memory cells in response to one or more programming pulses applied to the memory cells during an analog programming operation.
13. (Original) The method of claim 10, further comprising preconditioning the plurality of memory cells to an amorphous memory state.
“…the storage element material comprising chalcogenide; wherein forming the storage element material for one deck in the multi-deck memory array comprises forming a respective chalcogenide-containing material that has a thickness, or a composition, or both different from a respective chalcogenide-containing material of another deck in the multi-deck memory array…” – see claim 13.
14. (Original) The method of claim 10, further comprising storing a synaptic weight value based on storing respective analog information in each respective memory cell.
12. The method of claim 8 further comprising determining a synaptic weight value based on the output.
As can be seen from the above table, both the granted Patent 365 and the application recite the same foundational method: accessing a plurality of memory cells (where each cell has different programming sensitivities), and dealing with the storage and reading of analog information. The application introduces the step of "applying one or more programming pulses" to store the analog information. The use of programming pulses is known in the art as the fundamental mechanism for altering threshold voltages or writing states in memory cells. Reciting the application of a pulse to achieve the stored analog information is an inherent or obvious step to achieve the analog storage claimed in Patent 365. The application omits the specific multi-deck architecture and the use of different storage materials on different decks (which are defined in Patent 365). Omitting a specific material limitation or structural feature and claiming the remaining broader method is generally considered an obvious variation. Therefore, the patent protections have been granted to the earlier filed patent application.
For similar reasons, claims 11- 14 are rejected over claims 6, 8, 9, 12 and 13 of patent ‘365.
Claims 15-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8 and 10-12 of U.S. Patent No. 12080365 [‘365]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘365
15. (Original) A method comprising: accessing a plurality of memory cells each respective memory cell in the plurality of memory cells with a respective programming sensitivity different from the respective programming sensitivity of other cells in the plurality; reading from each respective memory cell analog information programmed in the respective memory cells; combining the analog information read from each respective memory cell; and providing an output based on combining the analog information.
8. A method comprising: accessing a plurality of memory cells in a multi-deck memory array, each respective memory cell in the plurality of memory cells having a programming sensitivity different from programming sensitivities of other cells in the plurality of memory cells, the respective memory cells being on different decks of the multi-deck memory array; reading, from the each respective memory cell, analog information programmed in the plurality of memory cells; combining the analog information read from the each respective memory cell, wherein the respective memory cells include a first memory cell and a second memory cell, comprising of different storage material; providing an output based on combining the analog information; and a first storage element of the first memory cell comprises a first storage material; and a second storage element of the second memory cell comprises a second storage material different from the first storage material.
16. (Original) The method of claim 15, wherein accessing the plurality of memory cells comprises biasing respective access lines coupled to respective memory cells on different decks of a multi-deck memory array.
“…, the respective memory cells being on different decks of the multi-deck memory array; reading, from the each respective memory cell …: - see claim 13.
17. (Original) The method of claim 16, wherein reading comprises detecting one or more signals generated on one or more respective access lines coupled to the respective memory cells based at least in part on biasing the respective access lines; and determining analog values stored by the respective memory cell based at least in part on detecting the one or more signals.
10. The method of claim 9 wherein reading comprises detecting one or more signals generated on one or more respective access lines coupled to the respective memory cells based at least in part on biasing the respective access lines; and determining analog values stored by the respective memory cell based at least in part on detecting the one or more signals.
18. (Original) The method of claim 17, wherein detecting one or more signals comprises detecting a sub-threshold current associated with at least one respective access line coupled to respective memory cells.
11. The method of claim 10 wherein detecting one or more signals comprises detecting a sub-threshold current associated with at least one respective access line coupled to respective memory cells.
19. (Original) The method of claim 15, further comprising determining a synaptic weight value based on the output.
12. The method of claim 8 further comprising determining a synaptic weight value based on the output.
As can be seen from the above table, Patent 365 claims a broad method of forming a specific memory architecture, which inherently includes the step of operating/accessing it. The application claims the specific method of accessing, reading, combining, and outputting the analog information from that exact hardware. The method of using or operating an inherently disclosed apparatus is considered obvious in light of the apparatus itself. Therefore, the patent protections have been granted to the earlier filed patent application.
For similar reasons, claims 16-19 are rejected over claims 8 and 10-12 of patent ‘365.
Claims 20-23 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 13 and 14 of U.S. Patent No. 12080365 [‘365]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘365
20. (Original) A method comprising: forming a plurality of memory cells each respective memory cell in the plurality of memory cells with respective programming sensitivity different from the respective programming sensitivity of other memory cells in the plurality; and forming reading circuitry coupled to the plurality of memory cells the reading circuitry configured to read the respective memory cells and to provide an output based on a combination of respective analog information read from the respective memory cells.
13. A method comprising: forming a plurality of respective memory cells in a multi-deck memory array, each memory cell in the respective memory cells having a programming sensitivity different from programming sensitivities of other memory cells in the respective memory cells, the respective memory cells being on different decks of the multi-deck memory array; and forming reading circuitry coupled to the respective memory cells, the reading circuitry configured to read the respective memory cells and to provide an output based on a combination of respective analog information read from the respective memory cells; wherein forming the multi-deck memory array comprises, for each deck: forming a bottom access line material; forming a top access line material; and forming a storage element material between the bottom and the top access line materials, the storage element material comprising chalcogenide; wherein forming the storage element material for one deck in the multi-deck memory array comprises forming a respective chalcogenide-containing material that has a thickness, or a composition, or both different from a respective chalcogenide-containing material of another deck in the multi-deck memory array.
21. (Original) The method of claim 20, wherein forming the plurality of memory cells comprises forming a multi-deck memory array, the respective memory cells being on different decks of the multi-deck memory array.
“…forming the multi-deck memory array comprises, for each deck: forming a bottom access line material; forming a top access line material…” – see claim 13.
22. (Original) The method of claim 21, wherein forming the multi-deck memory array comprises, for each deck: forming a bottom access line material, forming a top access line material, and forming a storage element material between the bottom and the top access line materials, the storage element material comprising chalcogenide.
“…forming the storage element material for one deck in the multi-deck memory array comprises forming a respective chalcogenide-containing material that has a thickness, or a composition, or both different from a respective chalcogenide-containing material of another deck in the multi-deck memory array….” – see claim 13.
23. (Original) The method of claim 22, wherein forming the storage element material for one deck in the multi-deck memory array comprises forming a respective chalcogenide-containing material that has a thickness and/or a composition different from another thickness or composition of a respective chalcogenide-containing material of another deck in the multi-deck memory array.
“…forming the storage element material for one deck in the multi-deck memory array comprises forming a respective chalcogenide-containing material that has a thickness, or a composition, or both different from a respective chalcogenide-containing material of another deck in the multi-deck memory array…” – see claim 13.
As can be seen from the above table, claim 13 of the patent 365 claims a method of forming a multi-deck memory array that uses chalcogenide, where specific memory cells on different decks are structurally formed to have different programming sensitivities (achieved by varying the thickness and/or composition of the chalcogenide layer). Claim 20 of the application claims a method of forming a generic array of memory cells (it omits the structural specifics of how the different sensitivities are achieved and the "multi-deck" or "chalcogenide" structural limitations).
Because the application simply claims the broad concept of utilizing memory cells with varying programming sensitivities, which was already fully disclosed and claimed in Patent 365, the application is merely claiming a subset or a broader genus of what is already patented. Therefore, the patent protections have been granted to the earlier filed patent application.
For similar reasons, claims 21-23 are rejected over claims 13 and 14 of patent ‘365.
Claim Rejections- 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 7 and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ish-Shalom et al. [US Patent Application # 20140112077].
With respect to claim 1, Ish-Shalom et al. disclose a device comprising: a plurality of memory cells each respective memory cell in the plurality of memory cells with a respective programming sensitivity different from the respective programming sensitivity of other memory cells in the plurality [“…to program a group of the analog memory cells by writing respective analog values into the memory cells in the group …” - par. 0017]; and reading circuitry configured to read respective analog information programmed in the respective memory cells and to provide an output based on a combination of the respective analog information read from the respective memory cells [“…using a set of read thresholds so as to produce readout results, to calculate a measure of information entropy of the readout results…” – par. 0017; and, “…calculating the measure of the information entropy comprises calculating a mutual information for the readout results and for decoding results of the data.” – see claim 8].
With respect to claim 2, Ish-Shalom et al. disclose a multi-deck memory array, the respective memory cells being on different decks of the multi-deck memory array. See par. 0032.
With respect to claim 6, Ish-Shalom et al. disclose the reading circuit is configured to read respective analog information based at least in part on a respective resistance, a respective conductance or a respective threshold voltage of the respective memory cells. See pars. 0007, 0017 and 0032.
With respect to claim 7, Ish-Shalom et al. disclose the reading circuit is configured to non- destructively read respective analog information programmed in the respective memory cells. See pars. 0007, 0017 and 0032.
With respect to claim 9, Ish-Shalom et al. disclose the plurality of memory cells is configured to store a synaptic weight. Ish-Shalom et al. indicated that the memory cells are configured to store data. See pars. 0007, 0017 and 0032.
Claim(s) 15-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ish-Shalom et al. [US Patent Application # 20140112077].
With respect to claim 15, Ish-Shalom et al. disclose a method comprising: accessing a plurality of memory cells each respective memory cell in the plurality of memory cells [“…the measure of the information …” – see claim 8] with a respective programming sensitivity different from the respective programming sensitivity of other cells in the plurality [“…programming the group comprises storing in the memory cells data represented by the analog values…” – see claim 8]; reading from each respective memory cell analog information programmed in the respective memory cells [“…calculating the measure of the information…” – see claim 8]; combining the analog information read from each respective memory cell; and providing an output based on combining the analog information [“…calculating the measure of the information entropy comprises calculating a mutual information for the readout results and for decoding results of the data.” – see claim 8].
With respect to claim 16, Ish-Shalom et al. disclose accessing the plurality of memory cells comprises biasing respective access lines coupled to respective memory cells on different decks of a multi-deck memory array. See pars. 0017 and 0032.
With respect to claim 17, Ish-Shalom et al. disclose reading comprises detecting one or more signals generated on one or more respective access lines coupled to the respective memory cells based at least in part on biasing the respective access lines; and determining analog values stored by the respective memory cell based at least in part on detecting the one or more signals. Ish-Shalom et al. indicated the above process in the following paragraphs: “…Analog memory cells are typically read by comparing their storage values to one or more read thresholds... a data storage device includes a memory array including a target memory cell and one or more other memory cells. The device also includes a controller coupled to the memory array. The controller is configured to directly compute a reliability measure for at least one bit stored in the target memory cell of the memory array based on a voltage value associated with the target memory cell and based on one or more corresponding voltage values associated with each of the one or more other memory cells of the memory array.” See pars. 0007-0010.
With respect to claim 18, Ish-Shalom et al. disclose detecting one or more signals comprises detecting a sub-threshold current associated with at least one respective access line coupled to respective memory cells. Ish-Shalom et al. indicated the above process in the following paragraphs: “…Analog memory cells are typically read by comparing their storage values to one or more read thresholds... a data storage device includes a memory array including a target memory cell and one or more other memory cells. The device also includes a controller coupled to the memory array. The controller is configured to directly compute a reliability measure for at least one bit stored in the target memory cell of the memory array based on a voltage value associated with the target memory cell and based on one or more corresponding voltage values associated with each of the one or more other memory cells of the memory array.” See pars. 0007-0010.
With respect to claim 19, Ish-Shalom et al. disclose determining a synaptic weight value based on the output. Ish-Shalom et al. indicated that the memory cells are configured to store data. See pars. 0007, 0017 and 0032.
Claim(s) 20-22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ish-Shalom et al. [US Patent Application # 20140112077].
With respect to claim 20, Ish-Shalom et al. disclose method comprising: forming a plurality of memory cells each respective memory cell in the plurality of memory cells with respective programming sensitivity different from the respective programming sensitivity of other memory cells in the plurality [“…to program a group of the analog memory cells by writing respective analog values into the memory cells in the group …” - par. 0017]; and forming reading circuitry coupled to the plurality of memory cells the reading circuitry configured to read the respective memory cells and to provide an output based on a combination of respective analog information read from the respective memory cells [“…using a set of read thresholds so as to produce readout results, to calculate a measure of information entropy of the readout results…” – par. 0017; and, “…calculating the measure of the information entropy comprises calculating a mutual information for the readout results and for decoding results of the data.” – see claim 8].
With respect to claim 21, Ish-Shalom et al. disclose forming the plurality of memory cells comprises forming a multi-deck memory array, the respective memory cells being on different decks of the multi-deck memory array. See pars. 0017 and 0032.
With respect to claim 22, Ish-Shalom et al. disclose forming the multi-deck memory array comprises, for each deck: forming a bottom access line material, forming a top access line material, and forming a storage element material between the bottom and the top access line materials, the storage element material comprising chalcogenide. Ish-Shalom et al. disclose various known analog memory cells, including the claimed recitations. See par. 0006.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 May 16, 2026
Prosecution Insights