DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin et al. (U.S. Patent Publication No. 2011/0164391).
Regarding claim 1, in Figure 15, Shin discloses a wiring board (200) comprising: a first wiring structure (comprising upper layers 180, 110, 120, 150, 193, 165, 160, 195,145) that includes a mounting surface (180) for a semiconductor element (upper component 140) and a back surface on an opposite side of the mounting surface; and a second wiring structure (comprising lower layers 180, 110, 120, 150, 193, 165, 160, 195,145) that is formed on the back surface of the first wiring structure, wherein the first wiring structure includes: thin film layers that include laminated wiring layers (145, 160, 165, 110) and laminated insulating layers (120, 150, 193); a cavity (130) that is formed by cutting out at least one of the insulating layers of the thin film layers in a direction toward the mounting surface (Figure 15); an electronic component (140) that is located in the cavity; and a filling resin layer (150) that fills the cavity, and further covers the electronic component.
Regarding claim 2, Shin discloses wherein the electronic component is located in the cavity that is formed by cutting out the at least one of the insulating layers of the thin film layers up to the mounting surface, and is exposed at the mounting surface (Figure 15).
Regarding claim 3, Shin discloses wherein the electronic component is located in the cavity that is formed by cutting out the at least one of the insulating layers of the thin film layers up to a position that does not reach the mounting surface, and is fixed onto one of the insulating layers of one of the thin film layers forming a bottom surface of the cavity (Figure 15).
Regarding claim 4, Shin discloses wherein the first wiring structure includes a plurality of electronic components including the electronic component; the plurality of electronic components are respectively located in a plurality of cavities including the cavity, each of the plurality of cavities being formed by cutting out the at least one of the insulating layers of the thin film layers in a direction toward the mounting surface; and the filling resin layer fills the plurality of cavities, and further covers the plurality of electronic components (Figure 15).
Regarding claim 5, Shin discloses wherein a thickness of the first wiring structure is equal to or less than a thickness of the second wiring structure (Figure 15).
Regarding claim 6, Shin discloses a support member, wherein the first wiring structure is formed on an upper surface of the support member in a state where the mounting surface faces an upper surface side of the support member (Figure 15).
Regarding claim 7, in Figure 15, Shin discloses a laminated wiring board (200) in which a wiring board is laminated on another wiring board, wherein the wiring board includes: a first wiring structure (comprising upper layers 180, 110, 120, 150, 193, 165, 160, 195,145) that includes a mounting surface (180) for a semiconductor element (upper component 140) and a back surface on an opposite side of the mounting surface; and a second wiring structure (comprising lower layers 180, 110, 120, 150, 193, 165, 160, 195,145) that is formed on the back surface of the first wiring structure, wherein the first wiring structure includes: thin film layers that include laminated wiring layers (145, 160, 165, 110) and laminated insulating layers (120, 150, 193); a cavity (130) that is formed by cutting out at least one of the insulating layers of the thin film layers in a direction toward the mounting surface (Figure 15); an electronic component (140) that is located in the cavity; and a filling resin layer (150) that fills the cavity, and further covers the electronic component.
Regarding claim 8, Shin discloses wherein an electrode pad is provided on an opposite surface of the second wiring structure, the opposite surface being on an opposite side of the first wiring structure, another electrode pad is provided on a surface of the other wiring board, and the electrode pad and the other electrode pad are electrically connected to each other, and the wiring board is laminated on the other wiring board (Figure 15).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST.
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TREMESHA W. BURNS
Primary Examiner
Art Unit 2847
/TREMESHA W BURNS/Primary Examiner, Art Unit 2847
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