Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/forms/. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-35 of U.S. Patent No. 12100454.
Current Application # 18819528
US Pat # 12100454
For example:
Claim 1:
1. An apparatus comprising: a tier including first memory cells, a control gate associated with the first memory cells, and a first dielectric material; first regions formed in the tier and coupled to each other, each of the first regions including a first material separated from the first dielectric material by a dielectric liner, the first material of each of the first regions surrounding a conductive material and separated from the conductive material by a second dielectric material; second regions formed in the tier and coupled to each other, at least one of the second regions including a second material contacting the first material of at least one region of the first regions, the second material of at least one of the second regions contacting the control gate; third regions formed in the tier and coupled to each other, at least one of the third regions including a third material contacting the first material of at least one region of the first regions; and a conductive line coupled to the third material of at least one of the third regions.
For example:
Claim 1:
5. An apparatus comprising: a first level including first memory cells, a first control gate for the first memory cells, and a first dielectric material; a second level including second memory cells, a second control gate for the second memory cells, and a second dielectric material; a first transistor including a first channel region located on the first level and separated from the first dielectric material by a first dielectric liner, the first transistor coupled between a first conductive region and a second conductive region, the first conductive region located on the first level and coupled to the first control gate; a second transistor including a second channel region located on the second level and separated from the second dielectric material by a second dielectric liner, the second transistor coupled between a third conductive region and a fourth conductive region, the third conductive region located on the second level and coupled to the second control gate; and a gate shared by the first and second transistors.
Even though the claims at issue are not identical but overall scope of the claims are identical and they are not patentably distinct from each other. For example, the above limitation “a conductive line coupled to the third material of at least one of the third regions.” in current application 18819528 and the limitation “third conductive region located on the second level and coupled to the second control gate” in US Pat # 12100454 are not identical but they anticipate each other. Because, as the conductive third region is coupled to the second control gate, there must be a conductive line. So, overall scope of the claims are identical and they are not patentably distinct from each other
Claims 1-20 would be allowable if the double patenting rejection set forth in this office action is overcome.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824