Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1, 8 and 15
b. Pending: 1-20
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Information Disclosure Statement
The information disclosure statement (IDS) is submitted on 9/12/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 10, 12, 13-14 and 18-20 of U.S. Patent No.10437321 (Reference Application). Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 and 2 of USP’321 is a combination of claims 1 and 5-7 of Instant Application as shown in the below table.
Instant Application
Reference Application
1. A device, comprising: a power management integrated circuit (PMIC), comprising: a first portion operable to manage power provided to outside of the power management integrated circuit; and a second portion operable to manage power provided to outside of the power management integrated circuit; wherein a function of the first portion in managing power is same as a function of the second portion.
1. A power management integrated circuit, comprising: a first set of circuits providing at least first functionalities in managing power; and a second set of circuits providing the first functionalities in managing power; wherein operations of the second set of circuits in providing the first functionalities consume less power than operations of the first set of circuits in providing the first functionalities; wherein, when operated in a first mode, the power management integrated circuit disables the second set of circuits and enables the first set of circuits to provide the first functionalities in managing power; and wherein, when operated in a second mode, the power management integrated circuit disables the first set of circuits and enables the second set of circuits to provide the first functionalities in managing power.
5. The device of claim 1, wherein the first portion and the second portion are configured to operate in different modes.
2. The power management integrated circuit of claim 1, wherein the first set of circuits further provides second functionalities when the power management integrated circuit is operated in the first mode; and the second set of circuits does not provide the second functionalities when the power management integrated circuit is operated in the second mode.
6. The device of claim 1, wherein the first portion is configured to provide the function of the first portion at a power consumption level lower than the second portion.
7. The device of claim 1, wherein the first portion is configured to operate at a frequency lower than the second portion to provide the function of the first portion.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12086015 (Reference Application). Although the claims at issue are not identical, they are not patentably distinct from each other because both set recite same claim limitations in slightly different language and spread over various claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Fung (US 20070101173).
Regarding independent claim 1, Fung discloses a device (Figs. 1-28), comprising:
a power management integrated circuit (PMIC), (Fig. 9 and [0101] describes management module 430) comprising:
a first portion operable to manage power provided to outside of the power management integrated circuit (Fig. 9 and [0101] describes management module 430 along with [0104] describes communication link coupling microcontrollers (.sub..mu.C) 442-1; together they form first portion. It provides power to outside server modules 402-1); and
a second portion operable to manage power provided to outside of the power management integrated circuit (Fig. 9 and [0101] describes management module 430 along with [0104] describes communication link coupling microcontrollers (.sub..mu.C) 442-N; together they form second portion. It provides power to outside server modules 402-N);
wherein a function of the first portion in managing power is same as a function of the second portion (Fig. 9 shows memory 408-1 and 408-N inside each server modules. Fig. 6 and [0069] describes that second (or secondary) switch module 104a-2 operates to provide the same function as the first module 104a-1).
Regarding claim 2, Fung discloses all the elements of claim 1 as above and further the function of the first portion corresponds to a function of a voltage regulator (Fig. 9 and [0103] describes voltage and frequency are regulated locally by the CPU using an activity monitoring scheme).
Regarding claim 3, Fung discloses all the elements of claim 1 as above and further the first portion is a voltage regulator (Fig. 10 and [0109] describes voltage regulator 324).
Regarding claim 4, Fung discloses all the elements of claim 1 as above and further the first portion is configured to convert an input power to the power management integrated circuit to a predetermined operating voltage of a component outside of the power management integrated circuit (Fig. 9 shows 402-1 is outside management module 430).
Regarding claim 5, Fung discloses all the elements of claim 1 as above and further the first portion and the second portion are configured to operate in different modes ([0104] describes that power management scheme may be interpreted in one aspect as providing a Mode1-to-Mode2 and Mode2-to-Mode1 power management scheme, where both Mode 1 and Mode 2 are active modes and the state of the CPU in either Mode 1 or Mode 2 is controlled locally by the CPU).
Regarding claim 6, Fung discloses all the elements of claim 1 as above and further the first portion is configured to provide the function of the first portion at a power consumption level lower than the second portion ([0104] describes that server modules may be monitored for activity and controlled globally to reduce power consumption while providing sufficient on-line capacity. It is noted that the power management may be effected by altering either or both of the CPU clock frequency 420 or the CPU voltage 416).
Regarding claim 7, Fung discloses all the elements of claim 1 as above and further the first portion is configured to operate at a frequency lower than the second portion to provide the function of the first portion ([0104] describes that server modules may be monitored for activity and controlled globally to reduce power consumption while providing sufficient on-line capacity. It is noted that the power management may be effected by altering either or both of the CPU clock frequency 420 or the CPU voltage 416).
Claims 8-14 recite same limitations of claim 1-7 in method format and henceforth rejected the same way.
Claims 15-20 recite same limitations of claim 1-7 and henceforth rejected the same way.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Smith et al. (US 20150022368) --- Fig. 3 teaches all the elements recited in claim 1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SULTANA BEGUM whose telephone number is (571)431-0691. The examiner can normally be reached M-F 8 am - 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at 571272 1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 3/31/2026