Prosecution Insights
Last updated: October 02, 2026
Application No. 18/819,725

Low Power State Implementation in a Power Management Circuit

Non-Final OA §103
Filed
Aug 29, 2024
Priority
Mar 12, 2018 — continuation of 10/437,321 +2 more
Examiner
BEGUM, SULTANA
Art Unit
2824
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Lodestar Licensing Group LLC
OA Round
2 (Non-Final)
94%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
519 granted / 555 resolved
+25.5% vs TC avg
Minimal +0% lift
Without
With
+0.3%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 9m
Avg Prosecution
21 currently pending
Career history
574
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
55.8%
+15.8% vs TC avg
§102
18.3%
-21.7% vs TC avg
§112
14.1%
-25.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 555 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of claim(s) to be treated in this office action: a. Independent: 1, 8 and 15 b. Pending: 1, 4-8, 11-15 and 17-20 Claims 1, 4-8, 11-15 and 17-20 have been amended and claims 2-3, 9-10 and 16 have been canceled. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. Terminal Disclaimer The terminal disclaimer filed on 6/17/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of U.S. Patent No.10437321 and U.S. Patent No. 12086015 have been reviewed and accepted. The terminal disclaimer has been recorded. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 4-8, 11-15 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 9720472) in view of Lee et al. (US 20160329734). Regarding independent claim 1, Park discloses a device (Figs. 1-10), comprising: a power management integrated circuit (PMIC) configured to receive an input power (Fig. 5 and (66) describes PMIC 320 is provided with an input power Vin 320a) and comprising: a first voltage regulator configured to convert the input power to a first output provided to a component outside of the power management integrated circuit, the first voltage regulator configured to operate at a first switching frequency (Figs. 6-7 and (71), (74), (76) describes PMIC 320 including plurality of converter 322-1, 322-2 and so on along with plurality of pulse width modulators (PWMs) configuring switching device outside the PMIC 320. Fig. 10 and (86) describes two modes: low frequency mode LFM, and high frequency mode HFM); and a second voltage regulator configured to convert the input power to a second output voltage provided to a second component outside of the power management integrated circuit, the second voltage regulator configured to operate at a second switching frequency (Fig. 5 and (66)-(67) describes PMIC 320 is provided with an input power Vin 320a of 5V to 12V, generates an enable signal to enable N1_EN, N2_EN, GPIO, I.sup.2C, etc., and provides a plurality of rails 320c of different sizes to each of the two SoCs. Herein, the plurality of rails 320c may be a first rail 320c1 to output a first power of 1V and 3 A, a second rail 320c2 to output a second power of 3.3V and 3 A. Fig. 10 and (86) describes two modes: low frequency mode LFM, and high frequency mode HFM); wherein the PMIC is configured to operate in a selectable mode of a plurality of selectable modes comprising a first mode and a second mode different from the first mode (Fig. 10 and (86) describes two different modes LFM and HFM). Lee explicitly teaches output provided to a component outside of the power management integrated circuit (Fig. 23 and [0182] describes that connectivity unit 1120 may perform wired or wireless communications with an external device). It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Lee to Park in order to provide voltage converter capable of increasing power transfer efficiency and performing stable mode transition as taught by Lee ([0004]). Regarding claim 4, Park and Lee together disclose all the elements of claim 1 as above and through Park further the first voltage regulator is configured to convert an input power to the power management integrated circuit to a predetermined operating voltage of the component outside of the power management integrated circuit (Fig. 10 and (85)-(86) describes to design or determine a value inside the predefined PMIC). Regarding claim 5, Park and Lee together disclose all the elements of claim 1 as above and through Park further the first voltage regulator and the second voltage regulator are configured to operate in different modes (Fig. 10 and (86) describes two different modes LFM and HFM). Regarding claim 6, Park and Lee together disclose all the elements of claim 1 as above and through Park further the first voltage regulator is configured to convert the input power to the first output at a power consumption level lower than the second voltage regulator (Fig. 5 and (66)-(67) describes PMIC 320 is provided with an input power Vin 320a of 5V to 12V, generates an enable signal to enable N1_EN, N2_EN, GPIO, I.sup.2C, etc., and provides a plurality of rails 320c of different sizes to each of the two SoCs. Herein, the plurality of rails 320c may be a first rail 320c1 to output a first power of 1V and 3 A, a second rail 320c2 to output a second power of 3.3V and 3 A). Regarding claim 7, Park and Lee together disclose all the elements of claim 1 as above and through Park further the first voltage regulator is configured to operate at a frequency lower than the second voltage regulator to convert the input power to the first output (Fig. 10 and (86) describes two modes: low frequency mode LFM, and high frequency mode HFM). Claims 8, 11-14 recite same limitations of claims 1, 4-7 but drafted in method format and henceforth rejected the same way. Claims 15, 17-20 recite same limitations of claims 1, 4-7 and henceforth rejected the same way. Response to Arguments Applicant’s arguments, see Remarks, filed on 6/17/2026, with respect to the rejection of independent claim 1 under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made over Park et al. (US 9720472) in view of Lee et al. (US 20160329734). Rejections are maintained at-least for above mentioned reasons. Details will be found under “Claim Rejections”. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SULTANA BEGUM whose telephone number is (571)431-0691. The examiner can normally be reached M-F 8 am - 5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at 571272 1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SULTANA BEGUM/Primary Examiner, Art Unit 2824 8/11/2026
Read full office action

Prosecution Timeline

Aug 29, 2024
Application Filed
Apr 03, 2026
Non-Final Rejection mailed — §103
Jun 17, 2026
Response Filed
Aug 13, 2026
Final Rejection mailed — §103
Sep 24, 2026
Response after Non-Final Action

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12744073
SEMICONDUCTOR MEMORY DEVICE PERFORMING REFRESH OPERATION
2y 5m to grant Granted Sep 22, 2026
Patent 12744069
ELECTRONIC DEVICE
2y 4m to grant Granted Sep 22, 2026
Patent 12744096
NONVOLATILE MEMORY DEVICE, STORAGE DEVICE AND METHOD OF OPERATING THE SAME
2y 3m to grant Granted Sep 22, 2026
Patent 12738310
MEMORY DEVICE INCLUDING ROW-HAMMER CELLS AND OPERATING METHOD THEREOF
2y 9m to grant Granted Sep 15, 2026
Patent 12738312
MEMORY DEVICE HAVING ROW DECODER CIRCUIT ARCHITECTURE
2y 3m to grant Granted Sep 15, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

2-3
Expected OA Rounds
94%
Grant Probability
94%
With Interview (+0.3%)
1y 9m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 555 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month