DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on August 5, 2026, has been entered.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
The amended drawings, filed August 5, 2026, are objected for failing to comply with 37 CFR 1.84(a)(1) and 37 CFR 1.84(I), which requires the drawings be in black, and that all drawings be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, solid black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines, however fine, to shading, and to lines representing cut surfaces in sectional views. Every letter, number, and figure label are pixelated because Applicant did not use black (RGB = 000), despite the letters, numbers, and figure labels appearing black to the naked eye. The dithering used to convert applicant's grayscale image to black and white will add white pixels to try to estimate applicant's "gray" color, and the final drawings may not print properly or may print with reduced quality. Therefore, applicant must be sure to use only black and white. Applicant may try the following process to correct the color content:
1. Open the drawings PDF file with Adobe Acrobat (a similar Adobe product may work, but the process has only been tested in Adobe Acrobat);
2. Click "File" and then click "Print";
3. Select "Adobe PDF" as the printer. If not available, "Microsoft Print to PDF" may also work, though this has not been tested. If neither option is available, this process may not be applicable, and applicant should try to find an alternate way to print in only black and white.
4. Uncheck "Print in grayscale (black and white)";
5. Uncheck "Save ink/toner";
6. Click "Advanced";
7. Under "Color Management", for the "Color Profile" field, select "Black & White" near the bottom of the list. The examiner also had "Treat grays as K-only grays" checked, and "Preserve Black" checked.
8. Click "OK" and then click "Print". The resulting PDF should comprise only black and white drawings. Please review the final drawings for potential unintended consequences of this process.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of copending Application No. 18/819,987 (Hereinafter Reference Application).
Regarding claim 1, the Reference Application teaches one or more processors comprising:
circuitry to:
perform a matrix multiply accumulate (MMA) instruction at a first MMA accelerator; and
in response to performing the MMA instruction, cause a plurality of portions of an MMA operation to be performed using a corresponding plurality of MMA accelerators, wherein the first MMA accelerator instructs the corresponding plurality of MMA accelerators to perform the plurality of portions of the MMA operation (Claim 1: Performing a plurality of portions of an MMA operation can be seen as performing multiple MMA operations. The processor cores are performing the plurality of MMA operations in parallel to accelerate the processing of the MMA instruction. Therefore, the processor cores are MMA accelerators).
Regarding claim 2, the Reference Application teaches the one or more processors of claim 1, wherein the circuitry is to cause a first operand of the MMA instruction exclusively to be stored in a tensor memory and a second operand of the MMA instruction is to be stored in a shared memory (see claim 2).
Regarding claim 3, the Reference Application teaches the one or more processors of claim 1, wherein the circuitry is to cause information used by the MMA operation to be exclusively stored in response to the MMA instruction (see claim 3).
Regarding claim 4, the Reference Application teaches the one or more processors of claim 1, wherein the circuitry is to further perform one or more second instructions concurrently with the MMA operation (see claim 4).
Regarding claim 5, the Reference Application teaches the one or more processors of claim 1, wherein the circuitry is to cause the plurality of portions to be exclusively stored in a plurality of shared memories and are each accessible by the plurality of MMA accelerators (see claim 5).
Regarding claim 6, the Reference Application teaches the one or more processors of claim 1, wherein the MMA instruction further comprises metadata that identifies an operating mode of the plurality of MMA accelerators (see claim 6).
Regarding claim 7, the Reference Application teaches the one or more processors of claim 1, wherein a single thread of a cooperative thread array performs the instruction that causes the plurality of MMA accelerators to perform the MMA operation (see claim 7).
Regarding claim 8, the Reference Application teaches a system comprising: one or more processors having one or more circuits to:
perform a matrix multiply accumulate (MMA) instruction at a first MMA accelerator; and
in response to performing the MMA instruction. cause a plurality of portions of an MMA operation to be performed using a corresponding plurality of MMA accelerators, wherein the first MMA accelerator instructs the corresponding plurality of MMA accelerators to perform the plurality of portions of the MMA operation (Claim 8: Performing a plurality of portions of an MMA operation can be seen as performing multiple MMA operations. The processor cores are performing the plurality of MMA operations in parallel to accelerate the processing of the MMA instruction. Therefore, the processor cores are MMA accelerators).
Regarding claim 9, the Reference Application teaches the system of claim 8, wherein the one or more processors are further to perform the MMA operation in response to the MMA instruction concurrently with one or more second operations (see claim 9).
Regarding claim 10, the Reference Application teaches the system of claim 8, wherein the one or more processors are to cause a first operand of the MMA instruction to be exclusively stored in a tensor memory and a second operand of the MMA instruction to be stored in a shared memory (see claim 10).
Regarding claim 11, the Reference Application teaches the system of claim 8, wherein the one or more processors are to store information used by the MMA operation exclusively in response to the MMA instruction (see claim 11).
Regarding claim 12, the Reference Application teaches the system of claim 8, wherein the one or more processors are to exclusively store the plurality of portions in a plurality of shared memories that are each accessible by the plurality of MMA accelerators (see claim 12).
Regarding claim 13, the Reference Application teaches the system of claim 8, wherein the MMA operation comprises performing matrix multiplication computations in response to the MMA instruction and accumulating results of the matrix multiplication computations in an exclusive storage (see claim 13).
Regarding claim 14, the Reference Application teaches the system of claim 8, wherein the plurality of portions correspond to a plurality of operands of the MMA operation (see claim 14).
Regarding claim 15, the Reference Application teaches a method comprising:
performing a matrix multiply accumulate (MMA) instruction at a first MMA accelerator; and
in response to performing the MMA instruction, causing a plurality of portions of an MMA operation to be performed using a corresponding plurality of MMA accelerators, wherein the first MMA accelerator instructs the corresponding plurality of MMA accelerators to perform the plurality of portions of the MMA operation (Claim 15: Performing a plurality of portions of an MMA operation can be seen as performing multiple MMA operations. The processor cores are performing the plurality of MMA operations in parallel to accelerate the processing of the MMA instruction. Therefore, the processor cores are MMA accelerators).
Regarding claim 16, the Reference Application teaches the method of claim 15, further comprising: exclusively storing a first operand of the MMA instruction in a tensor memory and a second operand of the MMA instruction in a shared memory (see claim 16).
Regarding claim 17, the Reference Application teaches the method of claim 15, further comprising: performing one or more second instructions concurrently with the MMA operation (see claim 17).
Regarding claim 18, the Reference Application teaches the method of claim 15, further comprising: using a single thread of a cooperative thread array to perform the MMA instruction that causes the plurality of MMA accelerators to perform the MMA operation (see claim 18).
Regarding claim 19, the Reference Application teaches the method of claim 15, wherein the plurality of portions correspond to a plurality of operands of the MMA operation (see claim 19).
Regarding claim 20, the Reference Application teaches the method of claim 15, further comprising storing a result of the MMA operation exclusively in a memory (see claim 20).
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5, 7-9, 12, 14-15, 17-19 are rejected under 35 U.S.C. 1023 as being unpatentable over Boswell et al. (US 20180321938 A1, see IDS filed November 19 2025) in view of Collier (US 20210374208 A1).
Regarding claim 1, Boswell teaches one or more processors (Fig. 4 and [0040]: Streaming multiprocessor (SM) 340 as the one or more processors) comprising:
circuitry to:
perform a matrix multiply accumulate (MMA) instruction at a first MMA accelerator (Figs. 1 and 4, [0108]: The MMA operation is to be performed by the SM 340 when an instruction to perform the MMA operation is executed. The circuitry within one of the SMs as the circuitry to perform the MMA instruction to be an MMA accelerator since it accelerates an MMA instruction by using a plurality of cores 450(L))
Boswell does not teach that in response to performing the MMA instruction, cause a plurality of portions of an MMA operation to be performed using a corresponding plurality of MMA accelerators, wherein the first MMA accelerator instructs the corresponding plurality of MMA accelerators to perform the plurality of portions of the MMA operation.
Note that the streaming multiprocessor uses a plurality of cores within to perform the MMA instruction (see [0108]). Furthermore, note that there may be more than one streaming multiprocessor in a texture processing cluster (see [0043])
Collier teaches to cause a plurality of portions of a matrix operation to be performed using a corresponding plurality of matrix accelerators (Figs. 1-2 and 11 and [0021-0031, 0054]: In response to a processor executing a matrix instruction, the processor (such as a CPU core 120) is to determine a plurality of matrix decompositions based on a predetermined number of available processor sockets 110 to perform the matrix instruction using parallelism. The matrix decompositions as the plurality of portions of a matrix operation resulting from the matrix instruction. The processor sockets as the plurality of matrix accelerators, since they are used to accelerate the matrix operation), wherein the first matrix accelerator instructs the corresponding plurality of matrix accelerators to perform the plurality of portions of the matrix operation ([0054]: The processor socket 110 to include the CPU core 120 to execute the matrix instruction as the first matrix accelerator, which instructs other available processor sockets to perform on a plurality of portions of a matrix operation).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Boswell with the teachings/techniques of Collier to have a processing core of a streaming multiprocessor to utilize other processing cores of other available streaming multiprocessors to execute the MMA instruction in parallel. By further decomposing matrices into smaller matrices and instructing other available streaming multiprocessors to take a decomposed matrix, additional parallelism would be realized, which would allow the instruction to be processed faster, which may be appreciated by one of ordinary skill.
Regarding claim 4, Boswell, in view of Collier, teaches the one or more processors of claim 1, wherein the circuitry is to perform one or more second instructions concurrently with the MMA operation (Boswell, Fig. 4 and [0052, 0108]: Each scheduler unit 410 within SM 340 includes one or more dispatch units 415, which then may dispatch two different instructions from the same warp in each clock cycle. Therefore, an MMA instruction and a second instruction may be executed concurrently).
Regarding claim 5, Boswell, in view of Collier, teaches the one or more processors of claim 1, wherein the circuitry is to cause the plurality of portions to be exclusively stored in a plurality of shared memories and are each accessible by the plurality of MMA accelerators (Boswell, Figs. 4 and 9, [0053, 0097-0098, 0107]: In the current combination, each SM 340 comprises of register file 420, which may implement one or more memory banks 910(0-N), wherein the register file is to store portions of the operands of an MMA operation. Each portion is stored as a plurality of elements in multiple registers, wherein each register may be located in one or more register banks. The plurality of elements are exclusively stored in the memory banks within the register file for when the MMA instruction is to be executed. Therefore, the plurality of portions of the MMA operation are stored within a shared memory, where each register file of each SM 340 makes up the plurality of memories accessible to their respective SM. Therefore, the plurality of portions of the MMA operation are accessible by the plurality of MMA accelerators. Memory banks as the plurality of shared memories).
Regarding claim 7, Boswell, in view of Collier, teaches the one or more processors of claim 1, wherein a single thread of a cooperative thread array performs the instruction that causes the plurality of MMA accelerators to perform the MMA operation (Boswell, [0051, 0108]: In the current combination, each warp contains a group of threads and schedules a group of threads for execution in parallel, where they cooperate on which units are to be used per thread to be executed, hence they make up as a cooperative thread array. An MMA operation can only be performed when it receives an MMA instruction from a thread containing the instruction. Therefore, a thread of a cooperative thread array performs an instruction that causes the streaming multiprocessor to perform the MMA operation and instruct a plurality of available SMs to also perform a portion of the MMA operation).
Regarding claim 8, the claim is mostly rejected for the same reasons as claim 1. Boswell also teaches a system (Fig. 3A and [0039]: GPC 250 as the system) comprising: one or more processors (Fig. 3A and [0040]: There exist a plurality of SMs 340 for the plurality of TPCs 320 that exist within GPC 250).
Regarding claim 9, Boswell, in view of Collier, teaches the system of claim 8, wherein the one or more processors are further to perform the MMA operation in response to the MMA instruction concurrently with one or more second operations (Boswell, Fig. 4 and [0052, 0108]: Each scheduler unit 410 within SM 340 includes one or more dispatch units 415, which then may dispatch two different instructions from the same warp in each clock cycle. Therefore, an MMA instruction, which performs the MMA operation, and a second instruction, which performs one or more operations, may be executed concurrently).
Regarding claim 12, the claim recites a system similar to the processor of claim 5. Therefore, the claim is rejected on the same premises.
Regarding claim 14, Boswell, in view of Collier, teaches the system of claim 8, wherein the plurality of portions correspond to a plurality of operands of the MMA operation (Boswell, Fig. 7 and [0082]: In the current combination, an input matrix A 710 and input matrix B 720 are the plurality of operands. Input matrix A and input matrix B may comprise of an 8x4 and 4x8 matrix, respectively. The plurality of operands are associated to the MMA operation. When performing the plurality of portions of the MMA operation, they will use the plurality of operands as part of the operation. Therefore, the plurality of portions correspond to a plurality of operands).
Regarding claim 15 and 17-18, the claims recite a method similar to the one or more processors of claims 1, 4, and 7, respectively. Therefore the claims are rejected on the same premises.
Regarding claim 19, the claim recites a method similar to the system of claim 14. Therefore the claim is rejected on the same premises.
Claim(s) 2-3, 10-11, 13, 16, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Boswell et al. (US 20180321938 A1, see IDS filed November 19 2025) in view of Collier (US 20210374208 A1) and Zhang et al. (WO 2025200693 A1, see IDS filed November 19 2025).
Regarding claim 2, Boswell, in view of Collier, teaches the one or more processors of claim 1, wherein the circuitry is to cause a second operand of the MMA instruction to be stored in a shared memory (Boswell, Fig. 4 and [0051, 0053]: The register file 420 within SM 340 is a temporary but global storage (i.e., a shared memory) used for operands needed for the functional units such as core 450(L). Therefore, in the current combination, a portion of the operand of the MMA instruction is fetched/stored in the register file).
Boswell, in view of Collier, does not teach that the first operand of the MMA instruction is exclusively stored in a tensor memory.
Zhang teaches that an operand of the MMA instruction is exclusively stored in a tensor memory (Fig. 4A and translated paragraph [0043]: The result of an MMA operation is stored in the tensor register file. The tensor register file as the tensor memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Boswell, in view of Collier, with the teachings of Zhang to have the circuitry store an operand of the MMA instruction in tensor memory. Given that matrix datasets consists of large amounts of data, one of ordinary skill would be motivated to provide a storage near an MMA unit performing the MMA operation as to avoid issues in relation to storing matrix data in memory.
Regarding claim 3, Boswell, in view of Collier, teaches the processor of claim 1.
Boswell, in view of Collier, does not teach that the circuitry is to cause information used by the MMA operation to be exclusively stored in response to the MMA instruction.
Zhang teaches that the information used by the MMA operation is to be exclusively stored in response to the MMA instruction (Fig. 4A and translated paragraph [0014, 0062-0063]: Tensor Register File is an exclusive storage made specifically for the matrix multiplication engine to exclusively store information of an MMA calculation (i.e., operation) such as matrix operands, which the operation can only be performed when an MMA instruction is executed).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Boswell, in view of Collier, with the teachings of Zhang to have information exclusively stored in response to the MMA instruction by the circuitry. One of ordinary skill would appreciate a separate storage unit for MMA operations as it'll contain all the necessary information that the MMA operations may need, which improves data access efficiency and decreases power consumption (see Zhang [0014]).
Regarding claim 10, the claim recites a system similar to the processor of claim 2. Therefore the claim is rejected on the same premises.
Regarding claim 11, the claim recites a system similar to the processor of claim 3. Therefore the claim is rejected on the same premises.
Regarding claim 13, Boswell, in view of Collier, teaches the system of claim 8, wherein the MMA operation comprises performing matrix multiplication computations in response to the MMA instruction (Boswell, Figs. 1 and 4, [0027, 0108]: The instruction that performs the MMA operation performs at least one dot product of corresponding pairs of vectors).
Boswell, in view of Collier, does not teach to place the accumulating results of the matrix multiplication computations in an exclusive storage.
Zhang teaches to store the accumulated results of the matrix multiplication computations in an exclusive storage (Fig. 4A and translated paragraph [0043]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Boswell, in view of Collier, with the teachings of Zhang to have stored the accumulated result of an MMA operation in an exclusive memory. Given that matrix datasets consists of large amounts of data, one of ordinary skill would be motivated to provide a storage near MMA accelerators performing portions of the MMA operation as to avoid issues in relation to storing matrix data in memory.
Regarding claim 16, the claim recites a method similar to the processor of claim 2. Therefore the claim is rejected on the same premises.
Regarding claim 20, Boswell, in view of Collier, teaches the method of claim 15.
Boswell, in view of Collier, does not teach to store a result of the MMA operation to be exclusively stored in a memory.
Zhang teaches that a result of the MMA operation is to be exclusively stored in a memory (Fig. 4A and translated paragraph [0043]: Results of the MMA operation are stored in the tensor register file).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Boswell, in view of Collier, with the teachings of Zhang to have stored the result of the MMA operation exclusively in memory. Given that matrix datasets consists of large amounts of data, one of ordinary skill would be motivated to provide a storage near MMA accelerators performing portions of the MMA operation as to avoid issues in relation to storing matrix data in memory.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Boswell et al. (US 20180321938 A1) in view of Collier (US 20210374208 A1) and Bhat et al. (“Matrix-Multiply Assist Best Practices Guide”, see IDS filed December 9, 2025).
Regarding claim 6, Boswell, in view of Collier, teaches the one or more processors of claim 1.
Boswell, in view of Collier, does not teach that the MMA instruction further comprises metadata that identifies an operating mode of the plurality of MMA accelerators.
Bhat teaches an MMA instruction comprising metadata that identifies an operating mode (Pages 14-15, Section 2.3.2 “Outer product instructions”: xvf32ger and xvi8ger are matrix instructions (with different opcodes to identify the difference between the two instructions) determines what data type is used when performing the MMA instruction. The opcodes as the metadata and the data type usage as the operating mode (i.e., 32-bit floating point matrix multiplication mode or 8-bit integer matrix multiplication mode)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Boswell, in view of Collier, with the teachings of Bhat to have the MMA instruction comprise of metadata that identifies an operating mode. One of ordinary skill may appreciate that the ability to switch between different data types improves the flexibility that one of ordinary skill has with the processor, especially if a processor is working with multiple data types at the same time.
Examiner’s Note
Applicant is advised that should claim 1 be found allowable, claim 8 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m). The differences between claim 1 and claim 8 is that claim 8 claims a system comprising of one or more processors having one or more circuits and claim 1 states that the circuitry within the one or more processors to perform an MMA instruction. However, these differences are not enough to differentiate the claims. Examiner recommends to insert a "system" component within claim 8.
Response to Arguments
Examiner acknowledges Applicant’s wishes to hold the NSDP rejection in abeyance pending the final disposition of the instant application and related applications. Currently, claims 1-20 stand rejected under Non-Statutory Double-Patenting in view of the amendments.
Applicant's arguments, see page 7, last paragraph to page 8, paragraph 2, filed August 5, 2026, with respect to the objections of the title of the invention, have been fully considered but they are not persuasive. Examiner believes the title is not descriptive of the invention, especially with respect to the additional amendments of claim 1. Note that MPEP 606.01 states that “[w]hen the title is not descriptive of the invention claimed, the examiner should require the substitution of a new title that is clearly indicative of the invention to which the claims are directed”, which “may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.” Examiner is offering the opportunity to Applicant to change the title of the invention. However, “[i]f a satisfactory title is not supplied by the applicant, the examiner may, at the time of allowance, change the title by an examiner’s amendment” (MPEP 606.01). The objection of the title is maintained.
Applicant’s arguments, see page 9, first paragraph to page 11, fourth paragraph, filed August 5, 2026, with respect to the rejection(s) of claim(s) 1-20 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejections has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art and a different interpretation of the prior art. See 103 rejections above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20250021618 A1: Choi teaches to divide input matrices between multiple nodes to perform matrix multiplication.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILIO ALCANTARA-RAMOS whose telephone number is (571)272-4211. The examiner can normally be reached Mon-Fri 8:30-5:00 PST.
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/E.A./Examiner, Art Unit 2183
/David J. Huisman/Primary Examiner, Art Unit 2183
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