DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities:
claim 1 has a typographical error in the last limitation of: a plurality of trenches in the first layer each including a conductive element electrically coupling the fingers to the second slayer [sic: layer]; and
claim 10 requires a bottom of the cavity being located at the face of “the substrate” closest to the first layer, whereas parent claim 8 defines “a semiconductor substrate.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7, 9-11, 14-17 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 requires “a cavity extending through the first layer, the bottom of the cavity exposing the substrate, and the conductive element including a third conductive layer.” It is not clear whether the third conductive element is part of the cavity of the first layer or whether it is part of the conductive element. For compact prosecution, the examiner will treat the third conductive layer (62) to be disposed on the walls of the cavity, as illustrated in Fig. 4 of the instant application.
Claim 9 recites the limitation of "third layer.” There is insufficient antecedent basis for this limitation in the claim. For compact prosecution, the examiner will treat the “third layer” to be the same as the “third conductive layer” that is defined in claim 7.
Claim 10 recites the limitation of "the third layer” and “the fourth layer” in lines 4-5. There is insufficient antecedent basis for these limitation in the claim. For compact prosecution, the examiner will treat the “third layer” to be any metal layer that is in contacting with the trench, and will treat the “fourth layer” to be the “fourth conductive layer” as defined in claim 8. This interpretation is supported by the conductive elements 66, for the third layer, and 76, for the fourth layer, as shown in Fig. 6 of the instant application.
Claim 11 recites the limitation of "third layer.” There is insufficient antecedent basis for this limitation in the claim. For compact prosecution, the examiner will treat the “third layer” to be the same as the “third conductive layer” that is defined in claim 7
Claim 14, and by extension, dependent claims 15-17 recite the limitation of “a respective conductive element electrically coupling a plurality of the [sic: missing element] to the second layer.” It is not clear what the conductive element is coupled to. For compact prosecution, the examiner will treat the fingers, as defined in claim 1, to be coupled to the conductive element.
Claim 20 requires “an electrical contact extending through the semiconductor layer, the semiconductor substrate and contacting the conductive layer.” It is not clear whether the comma between the semiconductor layer and the semiconductor substrate is an enumeration, therefore adding a new element (semiconductor substrate) or whether the electrical contact extends to both the semiconductor layer and the substrate. For compact prosecution, the examiner will use the latter interpretation.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 5-10, 12, 14 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Bothe (US 2022/0130985 A1) in view of Singh (US 2005/0269660 A1) and Romanczyk (WO 2025/034211 A1).
Regarding claim 1, Bothe teaches a device (100), comprising:
a first layer (116) having a first face (top surface of 116) and a second face (bottom surface of 116);
a second layer (112) below the first layer and coupled to the second face of the first layer;
a trench (trench of via 152 and trench of contact 126) in the first layer each including a conductive element (126) electrically coupling a source contact (125) to the second slayer.
Bothe further teaches the device to be an HEMT transistor (¶ [0005]) and further comprising:
the conductive contact is connected to one of a plurality of electrodes (122, 125, 123) on the first side of the first layer corresponding to the gate, source, and drain of the HEMT transistor (¶ [0082], [0059]);
the conductive contact being a top source contact (¶ [0082]);
a bottom source contact (145) disposed at the bottom of the second layer and coupled to the top source contact (¶ [0112]); and
the trench corresponding to the source of the HEMT transistor (since the top source contact 125 is connected to bottom source contact 145 through a via 152 in the trench).
However, Bothe does not teach the HEMT having the trench corresponding to the gate of the transistor, such that the gate has a top and a bottom contact.
Singh, in the same field of invention, teaches an HEMT transistor (¶ [0087]), wherein the gate has a top contact (194) and a bottom contact (101). Hence, Bothe in view of Singh teaches: the trench corresponds to the gate of the transistor.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Singh into the device of Bothe to reconfigure the HEMT device from having the source extend from the topside to the bottom side of the device to having the gate extend from the topside to the bottom side of the device by using a metallization of the trench to connect a topside gate contact and a backside gate contact. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of designing a voltage booster transistor that requires a backside gate contact (Singh ¶ [0013]-[0014], [0046]-[0049]), for the further purpose of improving the manufacturing yield and reducing costs by avoiding to hold the source to the ground (¶ [0011]-[0012]).
However, Bothe et al. do not teach the device comprising: a plurality of transistors having a plurality of fingers on the first side of the first layer, each finger corresponding to a gate of a plurality of transistors; and the trench to be one of a plurality of trenches of the transistors.
Romanczyk, in the same field of invention, teaches an HEMT device (see Title and Figs. 8-10) comprising:
a plurality of transistors (figures show multiple gates, sources, and drains) having a plurality of fingers (G) on the first side (top side of 116; see Fig. 1A) of the first layer (116), each finger corresponding to a gate of a plurality of transistors (see Figs. 8-10); and
the trench to be one of a plurality of trenches of the transistors (Bothe in view of Romanczyk teaches the gate trenches of Bothe to be under each gate region).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Romanczyk into the device of Bothe et al. to provide a plurality of transistors, with the gate of each transistor having a trench and a finger. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of designing a device used in high-frequency RF applications (Romanczyk ¶ [0002]) that require an array of HEMT transistors, thereby requiring a plurality of HEMT, with the source, drain, and gates of the transistors requiring multi-fingered connections, for the further purpose of improving the device performance and reducing the manufacturing cost due to defects (¶[0045]-[0046]) and to increase the device density (¶ [0072]).
Regarding claim 5, the device according to claim 1, wherein the first layer is GaN, of AlN or of AlGaN (Bothe ¶ [0054]).
Regarding claim 6, the device according to claim 1, wherein second layer is a semiconductor substrate (Bothe ¶ [0049]).
Regarding claim 7, the device according to claim 6, wherein each trench includes a cavity (cavity of via 152 parallel to layer 116; see Bothe Fig. 3) extending through the first layer, the bottom of the cavity exposing the substrate (Fig. 3 shows the cavity of layer 116 exposes the bottom of substrate 112), and the conductive element including a third conductive layer (via 152 next to the walls of 116; see 35 USC § 112b rejection above) extending over walls of the cavity and the bottom of the cavity.
Regarding claim 8, device according to claim 1, comprising a fourth conductive layer (145; Bothe Fig. 3) on a bottom (bottom surface of 112) of the second layer and separated from the first layer by the second layer, wherein the second layer is a semiconductor substrate (Bothe ¶ [0049]).
Regarding claim 9, device or the method according to claim 8, wherein the third layer is metal (¶ [0063], [0066]: 152 is a via, used to connect backside contact 145 to a topside contact 126; vias are known in the art to be comprised of a metal; see 35 USC § 112b rejection above).
Regarding claim 10, device according to claim 8, wherein each trench includes a cavity (cavity of via 152 that parallel to layer 116; see Bothe Fig. 3) extending through the first layer, a bottom of the cavity (bottom of the cavity above) being located at the face (top surface of 112 contacting the cavity of via 152) of the substrate closest to the first layer (cavity of via parallel to 116 is directly contacting the top surface of 112), the conductive element including a third conductive layer (via 152) extending over the walls and the bottom of the cavity and a portion (portion of via located parallel to layer 112) located in the substrate, in contact with the third layer (126) and in contact with the fourth layer (145; see also 35 USC § 112b rejection above).
Regarding claim 12, the device according to claim 6, wherein the semiconductor substrate is silicon or made of silicon carbide (Bothe ¶ [0049]: silicon carbide).
Regarding claim 14, Bothe teaches a method for manufacturing a device (100), comprising:
forming a first layer (116) on a second layer (112);
forming a conductive element (126) on a top side of the first layer;
forming a trench (trench of via 152 and trench of contact 126) extending from the first side (top side of 116) of the first layer to a second side (bottom side of 116) of the first layer; and
forming, in the trench, a respective conductive element (152) electrically coupling the conductive element (see 35 USC § 112 b rejection above) to the second layer (126 is coupled to 145, which contacts the second layer, using via 152).
Bothe further teach the method of making an HEMT transistor (¶ [0005]) further comprising of:
the conductive contact is part of a plurality of contacts (122, 125, 123) on the top side of the first layer corresponding to the gate, source, and drain of the HEMT transistor (¶ [0082]);
forming a bottom source contact (145) disposed at the bottom of the second layer and coupled to the top source contact (¶ [0112]);
wherein the trench corresponds to the source of the HEMT transistor (since top source contact 125 is connected to the bottom source contact 145 through the via 152 in the trench).
However, Bothe does not teach the method of making the HEMT transistor wherein the trench corresponding to the gate of the transistor, such that the gate has a top and a bottom contact.
Singh, in the same field of invention, teaches an HEMT transistor (¶ [0087]), wherein the gate has a top contact (194) and a bottom contact (101). Hence, Bothe in view of Singh teaches: the trench corresponds to the gate of the transistor.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Singh into the method of Bothe to reconfigure the HEMT device from having the source extend from the topside to the bottom side of the device to having the gate extend from the topside to the bottom side of the device by using a metallization of the trench to connect a topside gate contact and a backside gate contact. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of designing a voltage booster transistor that requires a backside gate contact (Singh ¶ [0013]-[0014], [0046]-[0049]), for the further purpose of improving the manufacturing yield and reducing costs by avoiding to hold the source to the ground (¶ [0011]-[0012]).
However, Bothe et al. do not teach the method comprising: forming a plurality of transistors; forming, on a first side of the first layer, a plurality of fingers each corresponding to a collective gate of a plurality of transistors; and the trench to be a plurality of trenches of the transistors.
Romanczyk, in the same field of invention, teaches a method of making an HEMT device (see Title and Figs. 8-10) comprising:
forming a plurality of transistors (figures show multiple gates, sources, and drains); forming, on a first side (top side of 116; see Fig. 1A) of the first layer (116), a plurality of fingers (G; Figs. 8-10) each corresponding to a collective gate (¶ [0046]: caterpillar gate configuration) of a plurality of transistors; and
the trench to be a plurality of trenches of the transistors (Bothe et al. in view of Romanczyk teaches the gate trenches of Bothe to be under each gate region).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Romanczyk into the method of Bothe et al. to provide a plurality of transistors, with the gate of each transistor having a trench and a finger. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of designing a device used in high-frequency RF applications (Romanczyk ¶ [0002]) that require an array of HEMT transistors, thereby requiring a plurality of HEMT, with the source, drain, and gates of the transistors requiring multi-fingered connections, for the further purpose of improving the device performance and reducing the manufacturing cost due to defects (¶[0045]-[0046]) and to increase the device density (¶ [0072]).
Regarding claim 18, Bothe teaches a device, comprising:
a semiconductor substrate (112; ¶ [0049]);
a semiconductor layer (116; ¶ [0054]) on the semiconductor substrate;
a transistor (¶ [0005]: HEMT transistor);
a first contact (125) extending in a first direction (horizontal direction) on the semiconductor layer and corresponding to a source (¶ [0082]) of the transistor;
a trench (trench of via 152) in the semiconductor layer;
a conductive element (152) in the trench in contact with the semiconductor substrate and electrically coupling the first contact to the semiconductor substrate (see Fig. 3).
Bothe further teach the first contact being a top contact of the source and a second contact (145) being the bottom contact of the source (¶ [0112]) and a gate contact (122) on the top surface of the semiconductor layer. However, Bothe does not teach the gate
However, Bothe does not teach the HEMT having the trench corresponding to the gate of the transistor, such that the gate has a top and a bottom contact.
Singh, in the same field of invention, teaches an HEMT transistor (¶ [0087]), wherein the gate has a top contact (194) and a bottom contact (101). Hence, Bothe in view of Singh teaches: the trench corresponds to the gate of the transistor.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Singh into the device of Bothe to reconfigure the HEMT device from having the source extend from the topside to the bottom side of the device to having the gate extend from the topside to the bottom side of the device by using a metallization of the trench to connect a topside gate contact and a backside gate contact. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of designing a voltage booster transistor that requires a backside gate contact (Singh ¶ [0013]-[0014], [0046]-[0049]), for the further purpose of improving the manufacturing yield and reducing costs by avoiding to hold the source to the ground (¶ [0011]-[0012]).
However, Bothe et al. do not teach the device further comprising: the transistor being part of a first group of transistors; the first contact being a first finger that extends in the first direction and corresponding to a collective gate of the first group of transistors; a second group of transistors; a second finger extending in the first direction on the semiconductor layer and corresponding to a collective gate of the second group of transistors; the trench disposed in between the first finger and the second finger; and the conductive element in the trench is electrically coupling the second fingers to the semiconductor substrate.
Romanczyk, in the same field of invention, teaches an HEMT device (see Title) comprising:
the transistor (T1; see Examiner Fig. 1) being part of a first group (G1) of transistors;
the first contact being a first finger (F1) that extends in the first direction (horizontal direction) and corresponding to a collective gate (upper set of 806/906; ¶ [0046]: caterpillar gate configuration) of the first group of transistors;
a second group of transistors (G2);
a second finger (F2) extending in the first direction on the semiconductor layer and corresponding to a collective gate (lower set of 806/906) of the second group of transistors;
the trench (B) disposed in between the first finger and the second finger (note: Bothe in view of Romanczyk teaches the trench of Bothe is place under the gate region of each transistor); and
the conductive element in the trench is electrically coupling the second fingers to the semiconductor substrate (Both in view of Romanczyk teaches the conductive element of Bothe to be also found in the second group of transistors).
PNG
media_image1.png
332
421
media_image1.png
Greyscale
Examiner Fig. 1. Taken from Romanczyk Fig. 8B
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Romanczyk into the device of Bothe et al. to add the transistor to a first group of transistor, with the first finger corresponding to a collective gate of the first group of transistors; add another second group of transistors with a second finger corresponding to each gate region of the transistor, with the trench between the first finger and second finger, and with the conductive element of the second finger electrically coupled to the substrate. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of designing a device used in high-frequency RF applications (Romanczyk ¶ [0002]) that require an array of HEMT transistors, thereby requiring a plurality of HEMT, with the source, drain, and gates of the transistors requiring multi-fingered connections, for the further purpose of improving the device performance and reducing the manufacturing cost due to defects (¶[0045]-[0046]) and to increase the device density (¶ [0072]).
Regarding claim 19, device of claim 18, comprising a conductive layer (145; Bothe Fig. 3) below and in contact with the semiconductor substrate.
Regarding claim 20, device of claim 19, comprising an electrical contact (152; Bothe Fig. 3) extending through the semiconductor layer, the semiconductor substrate (152 extends through both 116 and 112; see 35 USC § 112b rejection) and contacting the conductive layer.
Claims 2 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Bothe (US 2022/0130985 A1) in view of Singh (US 2005/0269660 A1) and Romanczyk (WO 2025/034211 A1) as applied to claim 1 and/or 14 above, and further in view Moens (US 2014/0264453 A1).
Regarding claim 2, Bothe et al. further teach the device according to claim 1, wherein the first layer is configured to be biased to a control voltage (Bothe ¶ [0008], [0021], [0023]-[0024]) of the transistors. However, Bothe et al. do not teach applying the same voltage to the second layer.
Moens, in the same field of invention, teaches applying a control voltage (¶ [0036]: Vth is the control voltage; ¶ [0030]: “current is then picked up by trench electrode 43 as a vertical current conductive component to substrate 11 and drain electrode 36”) to the second layer (11).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Moens into the device of Bothe et al. to apply the control voltage to the second layer. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of improving the device performance by eliminating electro-migration issues (Moens ¶ [0030]).
Furthermore, the recitation of configuring the second layer by biasing a control voltage is a recitation of a process-by-process claim. "[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). See MPEP § 2113 (I).
Regarding claim 15, Bothe et al. further teach the device according to claim 14, wherein the first layer is configured to be biased to a control voltage (Bothe ¶ [0008], [0021], [0023]-[0024]) of the transistors. However, Bothe et al. do not teach applying the same voltage to the second layer.
Moens, in the same field of invention, teaches applying a control voltage (¶ [0036]: Vth is the control voltage; ¶ [0030]: “current is then picked up by trench electrode 43 as a vertical current conductive component to substrate 11 and drain electrode 36”) to the second layer (11).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Moens into the device of Bothe et al. to apply the control voltage to the second layer. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of improving the device performance by eliminating electro-migration issues (Moens ¶ [0030]).
Furthermore, the recitation of configuring the second layer by biasing a control voltage is a recitation of a process-by-process claim. "[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). See MPEP § 2113 (I).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Bothe (US 2022/0130985 A1) in view of Singh (US 2005/0269660 A1) and Romanczyk (WO 2025/034211 A1) as applied to claim 8, and further in view of Tsai (US 10,153,273 B1).
Regarding claim 11, Bothe et al. teach the device according to claim 8, but do not teach: wherein the third layer is separated from the first layer by a fifth layer of insulating material.
Tsai, in the same field of invention, teaches the third layer (157 in Fig. 1B is analogous to the via 152 of Bothe Fig. 3; see 35 USC § 112b rejection above) is separated from the first layer (160; Col. 6, Ln1-5: 160 is a channel for HEMT 102; see also method Fig. 17) by a fifth layer (315) of insulating material (Col.4, Ln, 55-56: 315 is an isolation region).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Tsai into the device of Bothe et al. to add an insulating material between the third layer and the first layer. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of using the HEMT device (102; Tsai Col. 6, Ln. 25-30) in tandem with a MESHFET (101) and a MIM capacitor (142), which requires electrical isolations between the third layer and the first layer.
Claims 13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Bothe (US 2022/0130985 A1) in view of Singh (US 2005/0269660 A1) and Romanczyk (WO 2025/034211 A1) as applied to claim 1 and/or 15 above, and further in view of Trang (US 2020/0020779 A1).
Regarding claim 13, Bothe et al. teach the device according to claim 1, but does not teach: wherein each conductive element is coupled to the fingers by tracks and vias of an interconnection network.
Trang, in the same field of invention, teaches a device (Fig. 2) wherein each finger (example: 215; alternatively, 210) is coupled to tracks (235, 231; alternatively, 225, 221) and vias (238, 237; alternatively, 228, 227) of an interconnection network (see ¶ [0006], ¶ [0071]-[0072]). Hence, Moens et al. in view of Trang teach: wherein each conductive element is coupled to the fingers by tracks and vias of an interconnection network.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Trang into the device of Bothe et al. to connect each conductive element to tracks and vias of an interconnection network. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of using a redistribution layer to connect densely-spaced fingers of each overhanging pad (375; see Moens Fig. 3) to pads (221, 231; see Trang Fig. 2) that would be used to connect these pads to external circuits (Trang ¶ [0071]-[0072]).
Regarding claim 16, Bothe et al. teach the method of claim 15, but does not teach the method comprising forming a metal interconnection structure electrically coupling each finger to at least one of the conductive elements.
Trang, in the same field of invention, teaches a method (Fig. 2) of forming a metal interconnection structure (235&231; alternatively, 225, 221; see ¶ [0006], ¶ [0071]-[0072]) electrically coupling each finger (215; alternatively, 210). Hence, Moens et al. in view of Trang teaches: forming a metal interconnection structure electrically coupling each finger to at least one of the conductive elements.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Trang into the device of Bothe et al. to connect each conductive element to tracks and vias of an interconnection network. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of using a redistribution layer to connect densely-spaced fingers of each overhanging pad (375; see Moens Fig. 3) to pads (221, 231; see Trang Fig. 2) that would be used to connect these pads to external circuits (Trang ¶ [0071]-[0072]).
Allowable Subject Matter
Claims 3-4 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if rewritten to any overcome the 35 USC § 112b rejection.
Regarding claim 3, Romanczyk further teaches the device according to claim 1, where
the device according to claim 1, wherein the transistors are arranged in rows (each horizontal line of source/drains in Fig. 8-9), the transistors of the same row having a collective gate (806) corresponding to a same finger (gate of each transistor connected to 806),
However, no prior art was found to anticipate or render obvious:
the rows being arranged in columns, the columns being separated, two by two, by a trench, the conductive element of each trench separating two columns and being coupled to one end of each of the fingers of the two columns.
Regarding claim 17, Romanczyk further teaches the method according to claim 14, wherein the transistors are arranged in rows (each horizontal line of source/drains in Fig. 8-9), the transistors of the same row having a collective gate (806) corresponding to a same finger (gate of each transistor connected to 806),
However, no prior art of record was found to anticipate or render obvious:
the rows being arranged in columns, the columns being separated, two by two, by a trench, the conductive element of each trench separating two columns and being coupled to one end of each of the fingers of the two columns.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Buth (DE-102020121333-A1) teaches gate runners (24) that connect multiple gate fingers (21) that are arranged in rows and columns. However, Buth does not appear to teach multiple transistors connected by these gate runners. Instead, the disclosure teaches the entire structure to be a singular transistor device (see abstract).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS YAP whose telephone number is (703)756-1946. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/JOHN M PARKER/Primary Examiner, Art Unit 2899
Prosecution Insights