Attorney’s Docket Number: 23GR10411US01/815063.541
Filing Date: 8/29/2024
Claimed Foreign Priority Date: 9/06/2023 (FR2309348)
Inventors: Troussier et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the application filed 8/29/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first
inventor to file provisions of the AIA . In the event the determination of the status of the application as
subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing
from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art
relied upon, and the rationale supporting the rejection, would be the same under either status.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the pins being electrically coupled to at least one of the I/O terminals, the at least one group of pins being coupled together, must be shown or the feature(s) canceled from the claim(s). In addition, wherein at least one of the pins of the package is electrically coupled to none of the other pins, must be shown or the feature(s) canceled from the claim(s).No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6, 10, and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 is recites the limitation "…the substrate…" in line 3. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, the line will be construed to recite “…a substrate…”.
Claim 10 is recites the limitation "…the group pins…" in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, the line will be construed to recite “…the at least one group of pins…”.
Claim 12 is recites the limitation "…the core region…" in line 1. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, the line will be construed to recite “…a core region…”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7-9, 13, 15-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu (US 20210111173 A1).
Regarding claim 1, Liu (see, e.g., figs. 1-3) shows all aspects of the instant invention, including an electrostatic discharge (ESD) protection device comprising:
A diode (e.g., ESD diode PN, see annotated fig. 1) including at least one first finger (e.g., p-doping region 122, see fig. 2);
At least one semiconductor electronic switch (e.g., PMOS plurality of fig. 2, see annotated fig. 1) electrically coupled in parallel (see, e.g., paragraph 16 “The pull-up circuit 120 includes a plurality of first transistors (e.g., the first transistor PMOS shown in FIG. 1)” + paragraph “The ESD diode PN and the pull-up circuit 120 are connected in parallel.”, also see fig. 2) with the diode (e.g., ESD diode PN, see fig. 2) and including at least one second finger (e.g., active area 102, see annotated fig. 1), wherein the at least one first finger (e.g., p-doping region 122, see fig. 2) and the at least one second finger (e.g., active area 102, see annotated fig. 1) extend substantially parallel to a first direction (e.g., vertical Y-direction of fig. 2) and are aligned with each other along the first direction (e.g., vertical Y-direction of fig. 2).
Regarding claim 2, Liu (see, e.g., figs. 1-3) shows wherein the semiconductor electronic switch (e.g., PMOS plurality of fig. 2, see annotated fig. 1) includes a plurality of second fingers (e.g., plurality of active areas 102) and the diode (e.g., ESD diode PN, see fig. 2) includes a plurality of first fingers (e.g., plurality of p-doping regions 122), each second finger (e.g., active area 102, see annotated fig. 1) of the semiconductor electronic switch (e.g., PMOS plurality of fig. 2, see annotated fig. 1) being aligned with one of the first fingers (e.g., p-doping region 122, see fig. 2) of the diode (e.g., ESD diode PN, see fig. 2) along the first direction (e.g., vertical Y-direction of fig. 2), forming together a pair of fingers (e.g., pair of fingers, see annotated fig. 1), the pairs of fingers (e.g., pairs of fingers in annotated fig. 1) being aligned with one another along a second direction (e.g., horizontal direction, see second direction of annotated fig. 1) substantially perpendicular to the first direction (e.g., vertical Y-direction of fig. 2).
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Annotated Fig. 1
Regarding claim 3, Liu (see, e.g., figs. 1-3) shows at least one resistor (e.g., resistor component 128) having a larger dimension (see, e.g., extension of resistor 128 in vertical vs horizontal direction) substantially parallel to the first direction (e.g., vertical Y-direction of fig. 2).
Regarding claim 4, Liu (see, e.g., figs. 1-3) shows wherein the semiconductor electronic switch (e.g., PMOS plurality of fig. 2, see annotated fig. 1) includes a GCPMOS (e.g., note coupled gate 104 in PMOS plurality).
Regarding claim 5, Liu (see, e.g., figs. 1-3) shows two connection terminals (see, e.g., paragraph 17 “A plurality of first terminals of the first transistors are coupled to a power source 800 and configured to receive a first voltage POWER. A plurality of second terminals of the first transistors are coupled to one terminals of the resistors Ru1˜Ru7 respectively. The other terminals of the resistors Ru1˜Ru7 are coupled to an input/output pad I/O.”) coupled to electrodes (e.g., metal contacts N2 + N3, also note N3 connects the peripheral switch region with the central diode region) of the semiconductor electronic switch (e.g., PMOS plurality of fig. 2, see annotated fig. 1) and of the diode (e.g., ESD diode PN, see fig. 2).
Regarding claim 7, Liu (see, e.g., figs. 1-3) shows wherein the at least one first finger (e.g., p-doping region 122, see fig. 2) of the diode (e.g., ESD diode PN, see fig. 2) includes lateral sides which are parallel to the first direction (e.g., vertical Y-direction of fig. 2) and aligned with lateral sides (e.g., lateral sides of annotated fig. 2) of the at least one second finger (e.g., active area 102, see annotated fig. 1) of the semiconductor electronic switch (e.g., some individual PMOS of PMOS plurality of fig. 2, see annotated fig. 1), wherein the lateral sides (e.g., lateral sides of annotated fig. 2) of the at least one second finger (e.g., active area 102, see annotated fig. 1) are parallel to the first direction (e.g., vertical Y-direction of fig. 2).
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Annotated Fig. 2
Regarding claim 8, Liu (see, e.g., figs. 1-3) shows all aspects of the instant invention including an integrated circuit comprising:
an electrostatic discharge (ESD) protection device (e.g., pull-up circuit 120) including:
a plurality of diodes (e.g., ESD diode PN plurality, see annotated fig. 1) each including a first finger (e.g., p-doping region 122, see fig. 2) extending in a first direction (e.g., vertical Y-direction of fig. 2); and a plurality of switches (e.g., PMOS plurality of fig. 2, see annotated fig. 1) each including a second finger (e.g., plurality of active areas 102) extending in the first direction (e.g., vertical Y-direction of fig. 2) and aligned in the first direction (e.g., vertical Y-direction of fig. 2) with a respective first finger (e.g., p-doping region 122 beneath each respective active area 102); and a plurality of input/output (I/O) terminals (e.g., input/output pad I/O, see fig. 2 or paragraphs 25-26) electrically coupled the ESD protection device (e.g., pull-up circuit 120).
Regarding claim 9, Liu (see, e.g., figs. 1-3) shows a core region (e.g., central core portion in annotated fig. 3 below), and an I/O circuit (see, e.g., fig. 3) arranged at the periphery of the core region (see, e.g., core region of annotated fig. 3 below) of the integrated circuit and including the ESD protection device (e.g., pull-up circuit 120).
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Annotated Fig. 3
Regarding claim 13, Liu (see, e.g., figs. 1-3) shows wherein each switch (e.g., some individual PMOS of PMOS plurality of fig. 2, see annotated fig. 1) and respective diode (e.g., ESD diode PN coupled with respective aforementioned PMOS, see annotated fig. 1) are electrically coupled in parallel (see, e.g., paragraph 16 “The pull-up circuit 120 includes a plurality of first transistors (e.g., the first transistor PMOS shown in FIG. 1)” + paragraph “The ESD diode PN and the pull-up circuit 120 are connected in parallel.”, also see fig. 2).
Regarding claim 15, Liu (see, e.g., figs. 1-3) shows wherein the switch (e.g., PMOS plurality of fig. 2, see annotated fig. 1) includes a GCPMOS (e.g., note coupled gate 104 in PMOS plurality).
Regarding claim 16, Liu (see, e.g., figs. 1-3) shows all aspects of the instant invention including an integrated circuit comprising:
an electrostatic discharge (ESD) protection device (e.g., pull-up circuit 120), the ESD protection device (e.g., pull-up circuit 120) including:
a plurality of pairs of fingers (e.g., pair of fingers, see annotated fig. 1), each pair of fingers (e.g., pair of fingers, see annotated fig. 1) including a first finger (e.g., p-doping region 122, see annotated fig. 1) and a second finger (e.g., plurality of active areas 102) extending in a first direction (e.g., vertical Y-direction of fig. 2) and aligned with each other along the first direction (e.g., vertical Y-direction of fig. 2);
a plurality of diodes (e.g., ESD diode PN plurality, see annotated fig. 1), each diode (e.g., individual diode strips of ESD diode PN, see fig. 2) including a respective first finger (e.g., any of p-doping regions 122 aligned with active areas 102), and
a plurality of switches (e.g., PMOS plurality of fig. 2, see annotated fig. 1), each switch (e.g., individual PMOS of PMOS plurality) including a respective second finger (e.g., any of active areas 102 aligned with p-doping region 122).
Regarding claim 17, Liu (see, e.g., figs. 1-3) shows wherein each first finger (e.g., p-doping region 122, see annotated fig. 1) is a first strip of semiconductor material (see, e.g., paragraph 23), wherein each second finger (e.g., individual active area of plurality of active areas 102) is a second strip of semiconductor material (e.g., note 102 is an active area of the PMOS).
Regarding claim 18, Liu (see, e.g., figs. 1-3) shows wherein each pair of fingers (e.g., pair of fingers, see annotated fig. 1) corresponds to one of the diodes (e.g., one of individual diode strips of ESD diode PN, see fig. 2) and one of the switches (e.g., one of individual PMOS plurality of fig. 2, see annotated fig. 1) electrically coupled in parallel (see, e.g., paragraph 16 “The pull-up circuit 120 includes a plurality of first transistors (e.g., the first transistor PMOS shown in FIG. 1)” + paragraph “The ESD diode PN and the pull-up circuit 120 are connected in parallel.”, also see fig. 2).
Regarding claim 19, Liu (see, e.g., figs. 1-3) shows wherein the ESD protection device (e.g., pull-up circuit 120) includes a resistor (e.g., resistor component 128) extending in the first direction (e.g., vertical Y-direction of fig. 2), and being wider in a second direction (see, e.g., annotated fig. 4 below, note there is a direction in which the resistor component is ‘wider’ than the first and second finger in any given direction (note the claim doesn’t specify the width difference refers to the first and second fingers in the same ‘second’ direction)) than the first (e.g., p-doping region 122, see annotated fig. 1) and second fingers (e.g., plurality of active areas 102).
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Annotated Fig. 4
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Arai (US 20100127330 A1).
Regarding claim 6, Liu (see, e.g., figs. 1-3) fails to show wherein the semiconductor electronic switch and the diode are configured to withstand an electrostatic discharge voltage having a value equal to a target ESD protection value for a substrate.
Arai (see, e.g., fig. 14), in a similar device to Liu, teaches a semiconductor electronic switch (e.g., MOS transistor 12) and a diode (e.g., protection diode 14) configured to withstand an electrostatic discharge voltage (see, e.g., paragraph 3 ”…there has been a semiconductor device in which a poly-silicon diode serving as an electrostatic breakdown protection element is formed on a substrate where a MOS transistor is formed, in order to protect the MOS transistor from electrostatic discharge (ESD) caused by external static electricity”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the ESD poly-silicon-to-substrate configuration of Arai within the device of Liu, in order to achieve the expected result of handling the electrostatic discharge issues within the device.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Arai further in view of Salcedo (US 20140167106 A1).
Regarding claim 10, Liu (see, e.g., figs. 1-3) fails to show a package including a plurality of pins, each electrically coupled to at least one of the I/O terminals, at least one group of pins being electrically coupled together, the ESD protection device coupled to the at least one group of pins or to each of the at least one groups of pins being configured to withstand together an electrostatic discharge voltage having a value equal to a target ESD protection value for the package.
Arai (see, e.g., fig. 14), in a similar device to Liu, teaches a semiconductor electronic switch (e.g., MOS transistor 12) and a diode (e.g., protection diode 14) configured to withstand an electrostatic discharge voltage (see, e.g., paragraph 3 ”…there has been a semiconductor device in which a poly-silicon diode serving as an electrostatic breakdown protection element is formed on a substrate where a MOS transistor is formed, in order to protect the MOS transistor from electrostatic discharge (ESD) caused by external static electricity”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the ESD poly-silicon-to-substrate configuration of Arai within the device of Liu, in order to achieve the expected result of handling the electrostatic discharge issues within the device.
Liu in view of Arai, however, fails to teach a package including a plurality of pins, each electrically coupled to at least one of the I/O terminals, at least one group of pins being electrically coupled together, the ESD protection device coupled to the group of pins or to each of the groups of pins.
Salcedo (see, e.g., fig. 1), in a similar device to Liu in view of Arai, teaches a plurality of pins (e.g., first signal pin 2a + second signal pin 2b + third signal pin 2c), each electrically coupled to an I/O terminal (see, e.g., paragraph 33 “…the first signal pin 2a is electrically connected to an input of the receiver 6, and the second and third signal pins 2b, 2c are electrically connected to outputs of the first and second drivers 7a, 7b, respectively.”), at least one group of pins (e.g., first signal pin 2a and second signal pin 2b) being electrically coupled together (see, e.g., fig. 1), the ESD protection device (e.g., protection devices 1a-1c) coupled to the at least one group of pins (e.g., first signal pin 2a and second signal pin 2b).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the pin package of Salcedo within the device of Liu in view of Arai, in order back to achieve the expected result of expanding the input/output signal interface (e.g., through the new pins) away from the I/O terminals as desired.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Arai further in view of Salcedo and Lee (US 20230042003 A1).
Liu (see, e.g., figs. 1-3) shows a core region (see, e.g., core region of annotated fig. 3).
Liu in view of Arai further in view of Salcedo, however, fails to teach wherein the core region includes one or more of a memory circuit and a controller.
Lee (see, e.g., fig. 11), in a similar device to Liu in view of Arai further in view of Salcedo, teaches a memory circuit (e.g., memory circuits 620A or 620B) and a controller (e.g., memory controller MC1).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the memory circuit and controller of Lee within the core region of Liu in view of Arai further in view of Salcedo, in order to achieve the expected result of providing memory capacity operations regarding the signals within the core region of the device (also see paragraph 73 of Lee).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Innami (US 20160233209 A1).
Regarding claim 14, Liu (see, e.g., figs. 1-3) shows wherein the ESD protection device includes a resistor (e.g., Ru1) coupled to a terminal (see, e.g., paragraph 17 “A plurality of first terminals of the first transistors are coupled to a power source 800 and configured to receive a first voltage POWER. A plurality of second terminals of the first transistors are coupled to one terminals of the resistors Ru1˜Ru7 respectively. The other terminals of the resistors Ru1˜Ru7 are coupled to an input/output pad I/O.”) of at least one of the switches (e.g., some individual PMOS of PMOS plurality of fig. 2, see annotated fig. 1).
Liu (see, e.g., figs. 1-3), however, fails to explicitly show wherein the terminal is a control terminal.
Innami (see, e.g., fig. 1), in a similar device to Liu, teaches a terminal (e.g., control terminal T3) is a control terminal.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the control terminal configuration of Innami within the terminal of Liu, in order to achieve the expected result of including control elements within the terminal of the device
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Liu (US 20170025407 A1)(hereinafter Liu2).
Regarding claim 20, Liu (see, e.g., figs. 1-3) shows each switch (e.g., PMOS plurality of fig. 2, see annotated fig. 1) has a gate terminal (e.g., gate 104).
Liu (see, e.g., figs. 1-3), however, fails to explicitly show wherein each switch includes a transistor having a body terminal coupled together.
Liu2 (see, e.g., fig. 1), in a similar device to Liu, teaches wherein a transistor (e.g., transistor 14) has a gate terminal (e.g., gate terminal 14G) and a body terminal (e.g., body terminal 14B).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the gate terminal and body terminal of Liu2 within each switch of Liu, in order to achieve the expected result of providing a reverse-bias junction to the active areas surrounding the terminal, allowing standard transistor operation within the device.
Allowable Subject Matter
Claim 11 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 11, the primary art of record, Liu (US 20210111173 A1) in view of Arai (US 20100127330 A1) further in view of Salcedo (US 20140167106 A1) neither discloses nor renders obvious wherein at least one of the pins of the package is electrically coupled to none of the other pins, the ESD protection device coupled to said at least one of the pins being configured to withstand alone an electrostatic discharge voltage having a value equal to the target ESD protection value for the package.
Conclusion
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/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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