DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3-6, 8, 10-12, 14-16, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shiraishi (U.S. Publication No. 2010/0208132 A1) in view of Chan et al. (U.S. Publication No. 2007/0291216 A1; hereinafter Chan)
With respect to claim 1, Shiraishi discloses a method for forming a semiconductor package comprising: providing a package substrate [50,55] having top and bottom major package substrate surfaces, wherein the top major package substrate surface includes a die region and an encapsulation region surrounding the die region with a gap between the die region and the encapsulation region (see Figure 7B); depositing an encapsulant [40] on the encapsulation region, the encapsulant includes first and second major encapsulant surfaces and inner sidewalls with a step profile (see Figure 3A), the second major encapsulant surface adheres to the top major package substrate surface, the encapsulant covers the encapsulation region and forms a cavity structure (see Figure 7B); attaching a die [25] on the die region, wherein the die includes first and second major die surfaces, the second major die surface is attached to the die region; attaching a protective cover [30] on the step of the cavity structure, wherein the protective cover and the cavity structure form a hermetic cavity with a predetermined cavity height over the die (see ¶[0049]).
Shirashi fails to disclose forming one or more cavity interlocks within the encapsulation region of the package substrate, wherein the one or more cavity interlocks are configured to improve the adhesion of the encapsulant to the package substrate; In the same field of endeavor, Chan teaches forming one or more cavity interlocks within the encapsulation region [240] of the package substrate [220], wherein the one or more cavity interlocks are configured to improve the adhesion of the encapsulant to the package substrate (See Figure 1-9; ¶[0043]; multiple orientations of interlocks). The implementation of cavity interlocks as taught by Chan increases the surface area of contact for the encapsulant, thereby increasing adhesion strength (See Chan ¶[0043]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 3, the combination of Shirashi and Chan discloses wherein the cavity interlock is a discontinuity disposed within the encapsulation region of the top package substrate surface (See Chan Figure 6).
With respect to claim 4, the combination of Shirashi and Chan discloses wherein the discontinuity extends to an inactive metal layer of the package substrate (see ¶[0035]).
With respect to claim 5, the combination of Shirashi and Chan discloses wherein the discontinuity is a recess discontinuity, a protruded discontinuity, or a combination thereof (See Chan Figure 6).
With respect to claim 6, the combination of Shirashi and Chan discloses wherein the discontinuity is a discrete, continuous, or semi-continuous discontinuity (See Chan Figure 1).
With respect to claim 8, the combination of Shirashi and Chan discloses wherein the recess discontinuity includes one or more processed inner surfaces for enhancing the adhesion of the encapsulant to the package substrate (See Chan Figure 1-9; ¶[0043]).
With respect to claim 10, the combination of Shirashi and Chan discloses wherein the combination of recess discontinuity and protruded discontinuity includes a protruded structure disposed in a recess, wherein the protruded structure includes a shaped anchor or a solder structure (see Chan Figure 9).
With respect to claim 11, the combination of Shirashi and Chan discloses wherein the discrete discontinuity includes a plurality of discontinuities distributed within the encapsulation region in a regular or an irregular pattern (See Chan Figure 1).
With respect to claim 12, Shirashi discloses a method for forming a semiconductor package comprising: providing a package substrate [50,55] having top and bottom major package substrate surfaces, wherein the top major package substrate surface includes a die region and an encapsulation region surrounding the die region with a gap between the die region and the encapsulation region (see Figure 7B); depositing an encapsulant [40] on the encapsulation region, the encapsulant includes first and second major encapsulant surfaces and inner sidewalls with a step profile, the encapsulant covers the encapsulation region and forms a cavity structure (See Figure 7B); attaching package bond pads [53] on the top major package substrate surface, wherein the package bond pads are disposed in the portion of a non-die region between the die region and the encapsulation region; attaching a die [25] on the die region, wherein the die includes first and second major die surfaces, the second major die surface is attached to the die region; providing wire bonds [54] to electrically connect the die to the package bond pads; attaching a protective cover [30] on the step of the cavity structure, wherein the protective cover and the cavity structure form a hermetic cavity with a predetermined cavity height over the die.
Shirashi fails to disclose forming one or more cavity interlocks within the encapsulation region. In the same field of endeavor, Chan teaches forming one or more cavity interlocks within the encapsulation region [240] (See Figure 1-9; ¶[0043]; multiple orientations of interlocks). The implementation of cavity interlocks as taught by Chan increases the surface area of contact for the encapsulant, thereby increasing adhesion strength (See Chan ¶[0043]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 14, the combination of Shirashi and Chan discloses wherein the cavity interlock is a discontinuity disposed within the encapsulation region of the top package substrate surface (See Chan Figure 6).
With respect to claim 15, the combination of Shirashi and Chan discloses wherein the discontinuity is a recess discontinuity, a protruded discontinuity, or a combination thereof (See Chan Figure 6).
With respect to claim 16, the combination of Shirashi and Chan discloses wherein the discontinuity is a discrete, continuous, or semi-continuous discontinuity (See Chan Figure 1).
With respect to claim 18, the combination of Shirashi and Chan discloses wherein the recess discontinuity includes one or more processed inner surfaces for enhancing the adhesion of the encapsulant to the package substrate (See Chan Figure 1-9; ¶[0043]).
With respect to claim 19, the combination of Shirashi and Chan discloses wherein the combination of recess discontinuity and protruded discontinuity includes a protruded structure disposed in a recess, wherein the protruded structure includes a shaped anchor or a solder structure (see Chan Figure 9). With respect to claim 20, the combination of Shirashi and Chan discloses wherein the discrete discontinuity includes a plurality of discontinuities distributed within the encapsulation region in a regular or an irregular pattern (see Chan Figure 1).
Claim(s) 2 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shirashi in view of Chan as applied to claims 1 and 12 above, and further in view of Hsu (U.S. Publication No. 2019/0172864 A1)
With respect to claim 2, the combination of Shirashi and Chan fails to disclose wherein the encapsulant is directly formed on the encapsulation region of the package substrate by transfer molding. In the same field of endeavor, Hsu teaches encapsulant [114] is directly formed on the encapsulation region of the package substrate by transfer molding (See ¶[0053]). Implementation of transfer molding to produce the encapsulant of Shirashi and Chan, as taught by Hsu, is a well appreciated technique in the art and effective in producing a high quality encapsulant that prevents ingress of contaminants and moisture (See Hsu ¶[0053]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 13, the combination of Shirashi and Chan wherein the encapsulant is directly formed on the encapsulation region of the package substrate by transfer molding.
In the same field of endeavor, Hsu teaches encapsulant [114] is directly formed on the encapsulation region of the package substrate by transfer molding (See ¶[0053]). Implementation of transfer molding to produce the encapsulant of Shirashi and Chan, as taught by Hsu, is a well appreciated technique in the art and effective in producing a high quality encapsulant that prevents ingress of contaminants and moisture (See Hsu ¶[0053]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 7 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shirashi in view of Chan as applied to claims 5 and 15 above, and further in view of Fan (U.S. Publication No. 2008/0296751 A1).
With respect to claim 7, the combination of Shirashi and Chan fails to disclose wherein the recess discontinuity is formed by laser etching or drilling. In the same field of endeavor, Fan teaches producing recess discontinuity is formed by laser etching or drilling (see Figure 2 and ¶[0015]). Implementing drilling to produce the recess discontinuity of Shirashi and Chan, as taught by Fan, is a well appreciated technique in the art and effective in producing the recesses necessary for increased adhesion (see ¶[0015]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 17, the combination of Shirashi and Chan fails to disclose wherein the recess discontinuity is formed by laser etching or drilling.
In the same field of endeavor, Fan teaches producing recess discontinuity is formed by laser etching or drilling (see Figure 2 and ¶[0015]). Implementing drilling to produce the recess discontinuity of Shirashi and Chan, as taught by Fan, is a well appreciated technique in the art and effective in producing the recesses necessary for increased adhesion (see ¶[0015]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shirashi in view of Chan as applied to claim 8 above, and further in view of Jeong et al. (U.S. Publication No. 2013/0193545 A1; hereinafter Jeong).
With respect to claim 9, the combination of Shirashi and Chan fails to disclose wherein the processed inner surface includes a roughened surface or a surface lined with an adhesive layer. In the same field of endeavor, Jeong teaches wherein the processed inner surface includes a roughened surface or a surface lined with an adhesive layer [220] (See Figure 19).
Implementation of the adhesive layer of Jeong within the cavity interlocks of Shirashi and Chan allows for increased adhesion and maintaining a hermetic seal of the cavity (See Jeong ¶[0087]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN HAN whose telephone number is (571)270-7546. The examiner can normally be reached 9.00-5.00PM PST.
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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