DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 20 January 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Tsuboi (US 2021/0242292), in view of Kim et al (US 2019/0295470; hereinafter Kim), and further in view of Takasugi (US 2020/0202771).
• Regarding claims 1 and 10, Tsuboi discloses a display device (figure 19) comprising:
pixels (elements 102 in figures 19 and 20) connected to writing scan lines (elements 106 in figures 19 and 20 and ¶ 50), initialization scan lines (elements 1901 in figures 19 and 20 and ¶ 104), data lines (elements 107 in figures 19 and 20 and ¶ 50), and emission control lines (elements 1401 in figures 19 and 20 and ¶ 82),
wherein a pixel located in an i-th pixel row (i is an integer greater than 0) and a j-th pixel column (j is an integer greater than 0) includes:
a first transistor (element 202 in figure 20 and ¶ 56) having a first electrode connected to a first node (note the relationship between elements 202, 1501, 1502, and 1503 in figure 20), a second electrode connected to a second node (note the relationship between elements 201, 202, 204, and 2001 in figure 20), and a gate electrode connected to a third node (note the relationship between elements 202, 203, 204, and 1502 in figure 20);
a second transistor (element 203 in figure 20 and ¶ 57) connected between a j-th data line among the data lines and the third node (note the relationship between elements 107, 202, 203, 204, and 1502 in figure 20), and configured to be turned on when a first scan signal is supplied to a first scan line among the writing scan lines (¶ 57);
a third transistor (element 1501 in figure 20 and ¶ 83) connected between a first power source line to which a voltage of a first driving power source is supplied and the first node (note the relationship between Vdd and elements 202, 1501, 1502, and 1503), and configured to be turned on when an emission control signal is supplied to a k-th emission control line (k is an integer greater than 0) (¶ 84);
a fourth transistor (element 2001 in figure 20 and ¶ 105);
a first capacitor connected between the first node and the third node (element 1502 in figure 20 and ¶s 83 and 92);
a second capacitor connected between the second node and the third node (element 204 in figure 20 and ¶ 55); and
a light emitting element connected between the second node and a second power source line to which a second driving power source is supplied (element 201 in figure 20 and ¶ 53).
However, Tsuboi fails to disclose the additional details of the display device.
In the same field of endeavor, Kim discloses where:
one horizontal period (figure 2) includes a first period and a second period directly after the first period (periods P2 and P3 in figure 2),
during the first period, the fourth transistor is configured to be set to a turned-on state, and the second and third transistors are configured to be set to a turned-off state (element T7 in figure 3 is turned on by signal GB during period P2 while elements T2 and T4 are turned off), and
during the second period directly after the first period, the second transistor is configured to be set to a turned-on state, and the third and fourth transistors are configured to be set to a turned-off state (element T2 in figure 3 is turned on by signal GW during period P3 while elements T4 and T7 are turned off).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Tsuboi according to the teachings of Kim, for the purpose of initializing the anode electrode of a light emitting diode (¶ 48). However, Kim also fails to disclose the additional details of the display device.
In the same field of endeavor, Takasugi discloses where the one horizontal period is a horizontal period in which a data signal is supplied to the pixel is defined by the first period and the second period (figure 2B and ¶s 59-87; where Scan(n-2) is equivalent to Scan(n) for pixels in which data is written two rows earlier; thus a data signal for a pixel two rows earlier is supplied to the pixel during a first period defined by Scan(n-2) having a low voltage while a data signal for a pixel in the current row supplied to the pixel during a second period defined by Scan(n) (see also claim 2 in the reference)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Tsuboi, as modified by Kim, according to the teachings of Takasugi, for the purpose of initializing an anode of a light emitting element and an auxiliary capacitor of a pixel and compensating for a voltage variation of a power voltage line while maintaining a low number of signals and fixed voltages (¶ 8).
• Regarding claims 2, 3, and 11, Tsuboi, in view of Kim and Takasugi, discloses everything claimed, as applied to claims 1 and 10. Additionally, Tsuboi discloses where:
Claims 2 & 11: the pixel located in the i-th pixel row and the j-th pixel column further includes:
the fourth transistor having:
a first electrode connected to the second node (note the relationship between elements 201, 202, 204, and 2001 in figure 20),
a second electrode electrically connected to a third power source line to which an initialization power source is supplied (note the relationship between elements 206 and 2001 in figure 20), and
configured to be turned on when a second scan signal is supplied to a second scan line (¶ 105).
Claim 3: the light emitting element is configured to be turned off when a voltage of the initialization power source is supplied to the second node (¶ 105).
Claims 4-6, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Tsuboi, in view of Kim and Takasugi, and further in view of Nathan et al (US 2004/0129933; hereinafter Nathan).
• Regarding claims 4-6, 12, and 13, Tsuboi, in view of Kim and Takasugi, discloses everything claimed, as applied to claims 1 and 10. Additionally, Tsuboi discloses where:
However, Tsuboi, in view of Kim and Takasugi, fails to disclose the additional details of the pixel.
In the same field of endeavor, Nathan discloses where:
Claims 4, 6, & 12: each of the first to fourth transistors is a MOSFET including a body electrode (each of elements T1 and T2 in figures 5A and 11 and ¶s 31-35, 40, and 41; where the disclosed top gate is seen to be equivalent to the claimed body electrode), and
a ground voltage is supplied to the body electrode (¶s 33 and 34).
Claims 5 & 13: each of the first to fourth transistors is an N-type transistor (note where figures 5A and 11 and ¶s 35, 40, and 41 indicate that the transistors in a pixel circuit may be either N-type or P-type and may have a grounded top gate/body electrode).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Tsuboi, as modified by Kim and Takasugi, according to the teachings of Nathan, for the purpose of yielding reliable and stable circuit operation by grounding parasitic capacitance (¶ 34).
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Tsuboi, in view of Kim and Takasugi, and further in view of Nitomi et al (US 2008/0309595; hereinafter Nitomi).
• Regarding claims 8 and 9, Tsuboi, in view of Kim and Takasugi, discloses everything claimed, as applied to claim 2. However, Tsuboi, in view of Kim and Takasugi, fails to disclose the additional details of the display device.
In the same field of endeavor, Nitomi discloses where:
Claim 8: a voltage of a data signal is supplied to the data line during the first and second periods (¶s 40, 70-72, and 77-82).
Claim 9: the horizontal period further includes a third period (the period between t9 and t10 in figure 5), and
during the third period after the second period,
the second and third transistors are configured to be set in a turned-on state (signals DS and WS during the period between t9 and t10 in figure 5 and ¶s 83-89) and
the fourth transistor is configured to be set to the turned-off state (signal AZ2 during the period between t9 and t10 in figure 5 and ¶s 83-89).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Tsuboi, as modified by Kim and Takasugi, according to the teachings of Nitomi, for the purpose of suppressing a drop of light emission luminance arising from an organic electroluminescent device leak within a signal writing period (¶s 15-18).
Allowable Subject Matter
Claims 14, 15, and 17-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, either alone or in combination, fails to teach or fairly suggest, in claim 14, where “a threshold voltage of the driving transistor is compensated based on the amount of voltage change at the first node transmitted by the first capacitor that occurs between a data signal writing period of the pixel and an emission period of the pixel and the amount of voltage change at the second node transmitted by the second capacitor that occurs between the data signal writing period of the pixel and the emission period of the pixel”, in combination with all the remaining limitations in the claim. Claims 15 and 17-20 are allowed based on their dependence from claim 14.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Closing Remarks/Comments
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN DANIELSEN whose telephone number is (571)272-4248. The examiner can normally be reached Monday-Friday 9:00 AM to 5:00 PM Eastern Time.
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/NATHAN DANIELSEN/Primary Examiner, Art Unit 2622