DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Tokita (US 2024/0121959).
With regards to claim 1, figs. 1B-1E of Tokita discloses a semiconductor memory device comprising: a bit line (“bit line”, par [0042]); a first stacked body (bottom 146 in fig. 1E) arranged above the bit line (“bit line”, par [0042]), the first stacked body (bottom half of 146 in fig. 1E) including a plurality of first insulating layers (bottom half of 132) and a plurality of first conductive layers 146 alternately stacked one by one in a first direction (bottom to top), the first stacked body (bottom half of 146) including a first stairs region (bottom half of (132, 146)) and a first bridge region 240; the first stairs region (bottom half of 146) in which the ends of the plurality of first conductive layers (bottom half of 146, fig. 1E) are stepped in a second direction hd1 intersecting the first direction (bottom to top in fig. 1E) in a center of the second direction hd1; and the first bridge region (240) arranged adjacent to the first stairs region (bottom half of 146 in fig. 1E) in a third direction hd2 intersecting the first (bottom to top, fig. 1E) and second directions hd1, and the first bridge region ( 240 in bottom half of 146) electrically connects memory cell regions (100A, 100B) on both sides of the first stairs region (bottom half of 146, fig. 1C) in the second direction hd1 for each of the plurality of first conductive layers 146, and a second stacked body (top half of 146) arranged above the first stacked body (bottom half of 146), the second stacked body (top half of 146) including a plurality of second insulating layers (top half of 132) and a plurality of second conductive layers (top half of 146) alternately stacked one by one in the first direction (bottom to top, fig. 1E), the second stacked body (top half of 146) including a second stairs region (top half of 146 in fig. 1C) and a second bridge region (top half of 146 in fig. 1E); the second stairs region (top half of 146 in fig. 1C) in which the ends S of the plurality of second conductive layers (top half of 146 in fig. 1C) are stepped S in the second direction hd1 in the center of the second direction hd1; and the second bridge region (top half of 146 in 240) arranged adjacent to the second stairs region (top half of 146 in fig. 1C) in the third direction hd2, and the second bridge region (top half of 126 in 240) electrically connects memory cell regions (100A, 100B) on both sides of the second stairs region (top half of 146 in fig. 1C) in the second direction hd1 for each of the plurality of second conductive layers (top half of 146), wherein a width of a lowest layer of the plurality of first conductive layers 146 of the first bridge region (bottom half 146 in 240) in the third direction hd2 is larger (lowest layer of 146 in 240 greater than lowest layer of top half of 146) than a width of a lowest layer of the plurality of second conductive layers (top half of 146) of the second bridge region (top of 146 in 240) in the third direction hd2.
With regard to claim 2, figs. 1B-1E of Tokita discloses that the width of the lowest layer of the plurality of second conductive layers (top half of 146, fig. 1E) of the second bridge region (top half of 146 in 240, fig. 1E) in the third direction hd2 is in the range of 40% or more and 80% (in 240 the middle 146 is about 80% of bottommost 146 ) or less with respect to the width of the lowest layer of the plurality of first conductive layers (bottom half of 146) of the first bridge region (bottom half 146 in 240) in the third direction hd1, which is 100%.
With regard to claim 3, figs. 1B-1E of Tokita discloses that a third stacked body 246 arranged above the second stacked body (top half of 146), the third stacked body 246 including a plurality of third insulating layers 246 and a plurality of third conductive layers 246 alternately stacked one by one in the first direction (bottom to top), the third stacked body 246 including a third stairs region 246 and a third bridge region (240 in 246); the third stairs region 246 in which the ends of the plurality of third conductive layers 246 are stepped in the second direction hd1 in the center of the second direction hd1; and the third bridge region (246 in 240) arranged adjacent to the third stairs region 246 in the third direction hd2, and the third bridge region (246 in 240) electrically connects memory cell regions (100A, 100B) on both sides of the third stairs region 246 in the second direction hd1 for each of the plurality of third conductive layers 246, wherein a width of a lowest layer (bottommost 246) of the plurality of third conductive layers 246 of the third bridge region (246 in 240) in the third direction hd2 is larger (bottommost layer of 246 larger than bottom layer of top half of 146)) than a width of a lowest layer of the plurality of second conductive layers (top half of 146) of the second bridge region (top half of 146 in 240) in the third direction hd2.
With regard to claim 4, figs. 1B-1E of Tokita discloses that the width of the lowest layer of the plurality of second conductive layers (bottom layer of top half of 146) of the second bridge region (bottom layer of top half of 146 in 240) in the third direction hd2 is in the range of 40% or more and 80% (bottom layer of top half of 146 in 240 about 40% of bottommost layer of 246 in 240) ) or less with respect to the width of the lowest layer of the plurality of third conductive layers 246 of the third bridge region (246 in 240) in the third direction hd2, which is 100%.
With regard to claim 5, figs. 1B-1E of Tokita discloses that the width of a lowest layer of the plurality of first conductive layers (bottom half of 146) of the first bridge region (bottom half of 146 in 240) in the third direction hd2 is larger than a width of a lowest layer (width of top layer of 146 in 240 along hd2) of the plurality of third conductive layers of the third bridge region (top layer of 146 in 240) in the third direction hd2.
With regard to claim 6, figs. 1B-1E of Tokita discloses that the width of the lowest layer of the plurality of third conductive layers (width of top layer of 146 in 240 along hd2) of the third bridge region (width of top layer of 146 in 240 along hd2) in the third direction hd2 is in the range of 50% (top layer of 146 in 240 along hd2 is about half of bottom layer 146 in 240) or more and less than 100% with respect to the width of the lowest layer of the plurality of first conductive layers (bottom layer of 146 in 240) of the first bridge region (bottom layer of 146 in 240) in the third direction hd2, which is 100%.
Conclusion
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/BENJAMIN TZU-HUNG LIU/Primary Examiner, Art Unit 2893
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