Prosecution Insights
Last updated: October 02, 2026
Application No. 18/820,588

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §102§103
Filed
Aug 30, 2024
Priority
Nov 01, 2023 — RE 10-2023-0149353
Examiner
CAMPBELL, SHAUN M
Art Unit
Tech Center
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
73%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
770 granted / 1058 resolved
+12.8% vs TC avg
Moderate +9% lift
Without
With
+8.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
31 currently pending
Career history
1089
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
56.5%
+16.5% vs TC avg
§102
25.2%
-14.8% vs TC avg
§112
12.9%
-27.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1058 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claims 1-19 are presented for examination. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 5-6 and 8-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nemouchi et al. (US Pub. No. 2018/0337252 A1), hereafter referred to as Nemouchi. As to claim 1, Nemouchi discloses a semiconductor (fig 1H) comprising: a metal nitride layer (fig 1H, 103; [0036]); a channel (119) on a surface the metal nitride layer (103), the channel comprising a two-dimensional (2D) semiconductor material ([0052]); a source electrode (105/115 on left side of channel 119) on a first side of the channel (119); a drain electrode (105/115 on right side of channel 119) on a second side of the channel (119); a gate insulating layer (121; [0053]) on the channel (119); and a gate electrode (123; [0054]) on the gate insulating layer (121) such that the gate insulating layer (121) is between the gate electrode (123) and the channel (119). As to claim 5, Nemouchi discloses the semiconductor device of claim 1 (paragraphs above), wherein the channel includes a material expressed as M2X2, where M2 represents at least one of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, or Re, and X represents at least one of S, Se, or Te ([0052]). As to claim 6, Nemouchi discloses the semiconductor device of claim 1 (paragraphs above), wherein the channel includes at least one of MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ZrS2, ZrSe2, HfS2, HfSe2, NbSe2, or ReSe2 ([0052]). As to claim 8, Nemouchi discloses the semiconductor device of claim 1 (paragraphs above), wherein the channel (119) is in direct contact with the metal nitride layer (103). As to claim 9, Nemouchi discloses the semiconductor device of claim 1 (paragraphs above), wherein the channel includes a stack of 1 or more and 10 or less 2D semiconductor material layers ([0052]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 10, 14, 15 and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nemouchi in view of Lin et al. (US Pub. No. 2023/0420250 A1), hereafter referred to as Lin. As to claim 10, Nemouchi discloses a method of manufacturing a semiconductor device (figs 1A-H), the method comprising: depositing a metal nitride layer (103; [0036]); forming a channel of a two-dimensional (2D) semiconductor material (119) from a metal element with a chalcogen element ([0052]); forming a source electrode on a first side of the channel (105 on left side of channel 119) and forming a drain electrode on a second side of the channel (105 on right side of channel 119); forming a gate insulating layer (121) on the channel (119); and forming a gate electrode (123) on the gate insulating layer (121) such that the gate insulating layer (121) is between the gate electrode (123) and the channel (119). Nemouchi does not disclose depositing a metal layer on the surface of the metal nitride layer and forming the 2D semiconductor material by reacting a metal of the metal layer with a chalcogen element. Nonetheless, Lin discloses a method of making a 2D semiconductor material by depositing a metal layer then reacting a metal of the metal layer with a chalcogen element ([0024]). It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to manufacture the 2D semiconductor material of Nemouchi using the process as taught by Lin since this will allow for the improved control of the number of sub-layers resulting from the by process by varying the amount of precursors introduced into the reaction chamber, as well as, the pressure and temperature during the process. As to claim 14, Nemouchi in view of Lin disclose the method of claim 10 (paragraphs above). Nemouchi further discloses wherein the channel includes a material expressed as M2X2, where M2 represents at least one of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, or Re, and X represents at least one of S, Se, or Te ([0052]). As to claim 15, Nemouchi in view of Lin disclose the method of claim 10 (paragraphs above). Nemouchi further discloses wherein the channel includes at least one of MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ZrS2, ZrSe2, HfS2, HfSe2, NbSe2, or ReSe2 ([0052]). As to claim 17, Nemouchi in view of Lin disclose the method of claim 10 (paragraphs above). Nemouchi further discloses wherein the channel (119) is disposed to be in direct contact with the metal nitride layer (103). As to claim 18, Nemouchi in view of Lin disclose the method of claim 10 (paragraphs above). Nemouchi further discloses wherein the forming the channel includes forming the channel to include a stack of 1 or more and 10 or less 2D semiconductor material layers ([0052]). As to claim 19, Nemouchi in view of Lin disclose the method of claim 10 (paragraphs above). Lin further discloses wherein the forming of the channel is performed using at least one of a chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) process ([0025]). Claim(s) 2-4 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nemouchi in view of Chen et al. (US Pub. No. 2025/0051908 A1), hereafter referred to as Chen. As to claim 2, Nemouchi discloses the semiconductor device of claim 1 (paragraphs above). Nemouchi does not disclose wherein the metal nitride layer includes a transition metal and nitrogen. Nonetheless, Chen discloses a liner that is formed of a metal nitride that includes a transition metal and nitrogen (fig 2B, layer 221; [0035]). It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the metal nitride liner of Chen between the channel and the insulating layer of Nemouchi since this will create a uniformly thick barrier layer with the sidewalls of the insulating layer and provide a template with a large grain size. As to claim 3, Nemouchi in view of Chen disclose the semiconductor device of claim 2 (paragraphs above). Chen further discloses wherein the metal nitride layer includes a material expressed as M1N, where M1 represents the transition metal and includes at least one of Mo, W, Nb, V, Ta, Ti, Zr, or Hf, and N represents the nitrogen ([0035]). As to claim 4, Nemouchi discloses the semiconductor device of claim 1 (paragraphs above). Nemouchi does not disclose wherein the metal nitride layer has a thickness greater than 0 and about 3 nm or less. Nonetheless, Chen discloses wherein the metal nitride layer has a thickness greater than 0 and about 3 nm or less ([0034]). It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the metal nitride liner of Chen between the channel and the insulating layer of Nemouchi since this will create a uniformly thick barrier layer with the sidewalls of the insulating layer and provide a template with a large grain size. As to claim 7, Nemouchi discloses the semiconductor device of claim 1 (paragraphs above). Nemouchi does not disclose wherein the metal nitride layer further includes carbon. Nonetheless, Chen discloses wherein the metal nitride layer further includes carbon ([0035]). It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the metal nitride liner of Chen between the channel and the insulating layer of Nemouchi since this will create a uniformly thick barrier layer with the sidewalls of the insulating layer and provide a template with a large grain size. Claim(s) 11-13 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nemouchi in view of Lin and further in view of Chen. As to claim 11, Nemouchi in view of Lin disclose the method of claim 10 (paragraphs above). Nemouchi in view of Lin does not disclose wherein the metal nitride layer includes a transition metal and nitrogen. Nonetheless, Chen discloses a liner that is formed of a metal nitride that includes a transition metal and nitrogen (fig 2B, layer 221; [0035]). It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the metal nitride liner of Chen between the channel and the insulating layer of Nemouchi since this will create a uniformly thick barrier layer with the sidewalls of the insulating layer and provide a template with a large grain size. As to claim 12, Nemouchi in view of Lin disclose the method of claim 10 (paragraphs above). Chen further discloses wherein the metal nitride layer includes a material expressed as M1N, where M1 represents the transition metal and includes at least one of Mo, W, Nb, V, Ta, Ti, Zr, or Hf, and N represents the nitrogen ([0035]). As to claim 13, Nemouchi in view of Lin disclose the method of claim 10 (paragraphs above). Nemouchi in view of Lin does not disclose wherein the metal nitride layer has a thickness greater than 0 and about 3 nm or less. Nonetheless, Chen discloses wherein the metal nitride layer has a thickness greater than 0 and about 3 nm or less ([0034]). It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the metal nitride liner of Chen between the channel and the insulating layer of Nemouchi since this will create a uniformly thick barrier layer with the sidewalls of the insulating layer and provide a template with a large grain size. As to claim 16, Nemouchi in view of Lin disclose the method of claim 10 (paragraphs above). Nemouchi in view of Lin does not disclose wherein the metal nitride layer further includes carbon. Nonetheless, Chen discloses wherein the metal nitride layer further includes carbon ([0035]). It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the metal nitride liner of Chen between the channel and the insulating layer of Nemouchi since this will create a uniformly thick barrier layer with the sidewalls of the insulating layer and provide a template with a large grain size. Pertinent Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub. No. 2025/0072058A1 and US Pub. No. 2025/0063770A1. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 9/9/2026
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Prosecution Timeline

Aug 30, 2024
Application Filed
Sep 11, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
73%
Grant Probability
81%
With Interview (+8.6%)
2y 6m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1058 resolved cases by this examiner. Grant probability derived from career allowance rate.

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