Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/30/2024 was filed after the mailing date of the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, and 7-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al, US 20220173106 A1 and further in view of OZAKI TORU, JP 2001094070 A
Choi teaches:
A semiconductor device comprising:
a substrate; (102)
a bit line (194) extending vertically on the substrate;
a transistor body portion (120BD) including a first source/drain region (122), a channel layer (124), and a second source/drain region (126) that are arranged in a first horizontal direction, wherein the first source/drain region (122) is electrically connected to the bit line;
gate electrode layers (184) extending in a second horizontal direction orthogonal to the first horizontal direction and on an upper surface and a lower surface of the channel layer (124);
a gate dielectric film (182) between the gate electrode layers; and
a cell capacitor (200) electrically connected to the second source/drain region and including a lower electrode layer (210), a capacitor dielectric film (220), and an upper electrode layer (230), wherein the transistor body portion (120BD) is between the cell capacitor (200) and the bit line (194) in the first horizontal direction, and
wherein the channel layer (120) is included in a pattern (120a and 120b) that comprises oxide layers on an upper portion and a lower portion of the channel layer, respectively, and silicon nitride layers between the channel layer and the oxide layers, respectively.
See Figures 13A-13B
In regards to claim 1, Choi fails to teach:
an insulating pattern in the substrate;
a bit line extending vertically on the substrate and in contact with the insulating pattern;
Ozaki teaches:
an insulating pattern (16) in the substrate (1);
a bit line (17) extending vertically on the substrate and in contact with the insulating pattern. See figures 1-9
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the above references, because when the potential of the pair of bit lines BL and / BL is made to swing while the switching transistor 46 of the memory cell is turned on, a potential is generated at both ends of the cell capacitor 44, and the plate potential is increased.( see machine translation)
Choi further teaches:
2. The semiconductor device of claim 1, wherein the pattern is provided at least
twice. In regards to claim 2, see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960)
3. The semiconductor device of claim 1, wherein the channel layer includes single
crystal silicon. In regards to claim 3, see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960)
4. The semiconductor device of claim 1, wherein the channel layer and the
substrate include a same material. (para 78)
5. The semiconductor device of claim 1, wherein the pattern is on the substrate,
and one of the oxide layers is at a lowermost end of the pattern. (see figure 13B)
7. The semiconductor device of claim 1, wherein the insulating pattern includes
silicon oxide. (See machine translation of Ozaki)
8. The semiconductor device of claim 1, wherein the silicon nitride layers have a
same thickness. (para 23-24 of Choi)
9. The semiconductor device of claim 1, wherein the oxide layers include silicon
oxide. (para 19-20 Choi)
10. The semiconductor device of claim 1, wherein the capacitor dielectric film (220) and
the upper electrode layer (230) are on an inner side surface, an inner lower surface, and an outer side surface of the lower electrode layer (210). Figure 16A and B
11. The semiconductor device of claim 1, wherein the lower electrode layer has a
hollow shape including a closed portion that faces the second source/drain region and an open portion opposite to the closed portion in the first horizontal direction, and
wherein the upper electrode layer is in an inner portion of the hollow shape of the lower
electrode layer. (para 008, 0080)
12. The semiconductor device of claim 1, wherein at least one of the gate electrode
layers has a planar T-shape including a top horizontal line that faces the second source/drain region and a vertical line that faces the first source/drain region. (para 007, 008, 0106-0108)
13. The semiconductor device of claim 1, wherein the pattern is provided four
times. . In regards to claim 13, see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960)
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al, US 20220173106 A1 in view of OZAKI TORU, JP 2001094070 A and in further view of KUGIMIYA KENJI, JP 2000195967 A
Choi and Ozaki fail to teach:’
6. The semiconductor device of claim 1, wherein an upper surface of the insulating
pattern protrudes upward beyond an upper surface of the substrate.
Kenji teaches:
6. The semiconductor device of claim 1, wherein an upper surface of the insulating
pattern (5) protrudes upward beyond an upper surface of the substrate. See Figures 1 -4.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the above references, because a highly reliable drain contact can be provided with a high manufacturing yield and negligible leakage current in the connecting parts. (abstract machine translation)
Claim(s) 14-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al, US 20220173106 A1 and further in view of Kenji (cited previously)
14. A semiconductor device comprising:
a plurality of transistor body (120BD) portions that are spaced apart from each other in a vertical direction on a substrate and extend in parallel to each other in a first horizontal direction, the plurality of transistor body portions including a first source/drain region (122), a channel layer (124), and a second source/drain region (126) that are arranged in the first horizontal direction;
a plurality of bit lines (194) that are spaced apart from each other in a second horizontal
direction orthogonal to the first horizontal direction on the substrate and extend in parallel to each other in the vertical direction, wherein a respective one of the plurality of bit lines (194) is electrically connected to the first source/drain region of at least one of the plurality of transistor body portions (120BD);
a plurality of gate electrode layers (184) that are spaced apart from each other in the vertical direction, extend in parallel to each other in the second horizontal direction, and are on at least an upper surface and a lower surface of the channel layer of at least one of the plurality of transistor body portions (120BD);
a gate dielectric film (182) between ones of the plurality of gate electrode layers; and
a plurality of cell capacitors (200) electrically connected to the second source/drain region (126) of the plurality of transistor body portions (120BD), respectively, and including a lower electrode layer (210), a capacitor dielectric film (220), and an upper electrode layer (230), wherein the channel layer (124) is included in a pattern that comprises a pair of second material layers (120b) between a pair of first material layers (120a) and the channel layer (124) between the pair of second material layers, and
wherein the pattern is provided at least two times, and the channel layer (124) includes single crystal silicon. See Figures 13A-13B, 18A, 20 , para 19-23 and in regards to the repeating pattern, see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960)
Choi fails to teach:
wherein the substrate includes an insulating pattern having an upper surface that protrudes upward beyond an upper surface of the substrate in the vertical direction
Kenji teaches:
wherein an upper surface of the insulating pattern (5) protrudes upward beyond an upper surface of the substrate. See Figures 1 -4.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the above references, because a highly reliable drain contact can be provided with a high manufacturing yield and negligible leakage current in the connecting parts. (abstract machine translation)
Choi further teaches
15.The semiconductor device of claim 14, wherein the pair of first material layers
include oxide, and the pair of second material layers include silicon nitride. (para 64)
16. The semiconductor device of claim 14, wherein the pattern is provided four
times. in regards to the repeating pattern, see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960)
17. The semiconductor device of claim 14, wherein the channel layer and the
substrate include a same material. (para 019-023)
18. The semiconductor device of claim 14, wherein the insulating pattern includes
silicon oxide and is in contact with a lower portion of at least one of the plurality of bit lines. (see figures 1-4 of Kenji)
19. The semiconductor device of claim 14, wherein each of the plurality of gate
electrode layers has a planar T-shape that is rounded concavely between a top horizontal line and a vertical line of the planar T-shape. (para 007, 008, 0106-0108)
20. A semiconductor device comprising:
a plurality of transistor body portions (120BD) that are spaced apart from each other in a vertical
direction on a substrate and extend in parallel to each other in a first horizontal direction, the plurality of transistor body portions (120BD) including a first source/drain region (122), a channel layer (124), and a second source/drain region (126) that are arranged in the first horizontal direction;
a plurality of bit lines (194) that are spaced apart from each other in a second horizontal
direction orthogonal to the first horizontal direction on the substrate, extend in parallel to each other in the vertical direction, wherein a respective one of the plurality of bit lines (194) is electrically connected to the first source/drain region (122) of at least one of the plurality of transistor body portions (102BD);
a plurality of gate electrode layers (184) that are spaced apart from each other in the vertical direction, extend in parallel to each other in the second horizontal direction, and are on at least an upper surface and a lower surface of the channel layer (124) of at least one of the plurality of transistor body portions; (120BD)
a gate dielectric film (182) between ones of the plurality of gate electrode layers;
a plurality of cell capacitors (200) including a lower electrode layer (210), an upper electrode layer (230) on the lower electrode layer, and a capacitor dielectric film (220) between the lower electrode layer and the upper electrode layer, wherein the lower electrode layer of a respective one of the plurality of cell capacitors is electrically connected to the second source/drain region (126) of a respective one of the plurality of transistor body portions (120BD), and wherein the lower electrode layer (210) of the respective one of the plurality of cell capacitors (200) has a hollow shape (para 008) including a closed portion that faces the second source/drain region of the respective one of the plurality of transistor body portions (102BD) and an open portion opposite to the closed portion in the first horizontal direction;
an oxide layer (120a) on the channel layer (124); and
a silicon nitride layer (120b) between the oxide layer and the channel layer (124),
wherein the channel layer includes single crystal silicon (para 019-0230),
Choi fails to teach:
and an upper surface of the insulating pattern protrudes upward beyond an upper surface of the substrate in the vertical direction.
Kenji teaches:
wherein an upper surface of the insulating pattern (5) protrudes upward beyond an upper surface of the substrate. See Figures 1 -4.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the above references, because a highly reliable drain contact can be provided with a high manufacturing yield and negligible leakage current in the connecting parts. (abstract machine translation)
Conclusion
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MICHAEL . LEBENTRITT
Primary Examiner
Art Unit 2893
/MICHAEL LEBENTRITT/Primary Examiner, Art Unit 2893
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