DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1, 3, 8-9 and 10-11 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. It is claimed, in part: wherein the first and second inverters are configured to operate reliably under voltage conditions higher than a positive supply voltage of the apparatus. (emphasis added) It is unknown and at best speculative what may be understood by operate reliably; while it would appear that no specific definition is offered for “reliably” in the specification, the Merriam-Webster Dictionary, 10th edition, defines it as “in a consistently good or accurate way.” It is, thus, open to interpretation what level of good or accurate is one the instant invention is aiming for. While in regard to claim 3, it is claimed: wherein a number of transistors of the stacked transistors is chosen at least partially to maintain voltage stress on a respective transistor of the stacked transistors within its respective tolerances. First, the claim expressly and clearly requires “a number of transistors of the stacked transistors,” yet, it then changes the scope of the claim by reciting: “is chosen.” It is unclear which of the number of stacked transistors (plural) “is chosen.” And, as claimed, it “is chosen” to “maintain a voltage stress on a respective transistor…” It is unclear what is meant by “a respective transistor of the stacked transistors.” FIG. 2 of the drawings of the instant Application discloses at least 8 transistors in stacked arrangement. Which one is “the chosen” one is unclear, and unclear is which one is the “respective transistor.” Moreover, the claim seems to be in contradiction with the specification; for example, at [0051] it is found: “This stacking allows for a division of voltage across the transistors, helping to manage the voltage stress within the devices” (emphasis added) And, [0054] discloses: “When the gates of N1B and N2B are driven by NBIAS, their source voltages are constrained to be a fraction of the drain voltage V.sub.D, limiting the voltage stress across them. (emphasis added) It seems the teachings in the specification are concerned with limiting or reducing voltage stresses, yet the claim seems to require maintaining voltage stress. It is one or the other, not both. While in regard to claim(s) 8 and 9, there does not seem to be antecedent basis for at least some of the claimed limitations: “the first access transistor;” and “the second access transistor.” While in regard to claim 10, it is unclear, possibly leading to any number of interpretations what may be meant by: “comprising one or more impedance elements arranged between one or more of the first node or the second node.” (emphasis added) Could this mean that the first node or the second node is in fact more than one? Just to make this point exceedingly clear: is it claimed that the first node is in fact more than one node; likewise, is it claimed that the second node is in fact more than one node? While in regard to claim 11, It seems the claim has a number of issues: first, it is unknowable what may be meant by “a commentary word line.” The Merriam-Webster Dictionary, 10th edition, defines “commentary” as an expression of opinions or offering of explanations about an event or situation; spoken account of an event or performance as it happens. Could it be possible that the claimed word line is capable of providing an account of an event as it happens? Moreover, the last paragraph of the claim seems to end abruptly: “where the logic.” This is found meaningless.
Claim(s) 2-10 and 12-16 depend from claim(s) 1 and 11, and as such are also rejected for the same reasons as found in the rejection to the base claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent/Publication No. 7504695 to Martelloni et al. (“Martelloni”) in view of U.S. Patent/Publication No. 7187597 to Trimberger (“Trimberger”).
As to claim 1, Martelloni teaches substantially the claimed invention, including: An apparatus (As found in at least Column 1, lines 23-25; to be noted, SRAM is embedded in circuitry, apparatus that include the SRAM and other circuitry) comprising: a first inverter and a second inverter cross-coupled between a first node and a second node to store a signal state represented by voltage values at the first node and the second node (As found in at least FIG. 5: first inverter M1/M3 and second inverter M2/M4, cross-coupled between first and second storage nodes K1 and K2 to store signal state represented by either voltage Vdd or Vss); a first access transistor to selectively couple the first node to a bit line and allow direct control of the first node during access operations (As found in at least FIG. 5: first access transistor M5 couples K1 to bit line BL selectively); and a second access transistor to selectively couple the second node to the bit line and allow direct control of the second node during access operations (As found in at least FIG. 5: second access transistor M7 couples K2 to bit line BL selectively).
Martelloni may not expressly teach wherein respective positive supply inputs of the first inverter and the second inverter to couple to a voltage supply associated with a higher voltage level than the positive supply voltage of the apparatus; wherein the first and second inverters are configured to operate reliably under voltage conditions higher than a positive supply voltage of the apparatus.
However, relevantly and complementarily, Trimberger teaches wherein respective positive supply inputs of the first inverter and the second inverter to couple to a voltage supply associated with a higher voltage level than the positive supply voltage of the apparatus; wherein the first and second inverters are configured to operate reliably under voltage conditions higher than a positive supply voltage of the apparatus (As found in at least FIG. 4 and Column 7, lines 33-38: supply of memory array 420, SRAM, higher than at least apparatus 401; 420 having a higher supply than at least 401, obviously works reliably; otherwise, the claimed invention in the reference would have been found lacking utility).
Martelloni and Trimberger are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory having cross-coupled inverters and operate at a supply level.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Martelloni as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Trimberger also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: providing a high supply voltage to an SRAM cell increases speed, data storage accuracy and at least reduces noise; while keeping other apparatuses at lower supply voltage helps reduce the overall power consumption.
Therefore, it would have been obvious to combine Martelloni with Trimberger to make the above modification.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent/Publication No. 7504695 to Martelloni et al. (“Martelloni”) in view of U.S. Patent/Publication No. 7187597 to Trimberger (“Trimberger”), and further in view of 7332780 to Matsuda et al. (“Matsuda”).
As to claim 2, Martelloni as modified teaches substantially the claimed invention, the teachings may not expressly include wherein one or both of the first inverter or the second inverter includes stacked transistors to divide voltage across respective ones of the stacked transistors.
Matsuda, relevantly and complementarily teaches wherein one or both of the first inverter or the second inverter includes stacked transistors to divide voltage across respective ones of the stacked transistors (As found in at least FIG. 5: both inverters include stacked transistors).
Martelloni as modified Matsuda are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory having cross-coupled inverters and operate at a supply level.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Martelloni as modified as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Matsuda also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: as found in at least Column 8, lines 26-29; referring to FIG. 2, one inverter of the two in FIG. 5.
Therefore, it would have been obvious to combine Martelloni as modified with Matsuda to make the above modification.
Claim(s) 4, 5, 7 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent/Publication No. 7504695 to Martelloni et al. (“Martelloni”) in view of U.S. Patent/Publication No. 7187597 to Trimberger (“Trimberger”), and further in view of US 20190237139 to McCollum et al. (“McCollum”).
As to claim 4, at least McCollum teaches at least one input to receive a bias voltage to bias gates of one or more transistors of one or both of the first inverter or the second inverter (As found in at least FIG. 1A: cross-coupled inverters include at least one input bias, such as Nbias, to bias gates on one or both inverters).
Martelloni as modified and McCollum are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory having cross-coupled inverters and operate at a supply level.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Martelloni as modified as set forth in this Office action and as found in the reference with the relevant and complementary teachings of McCollum also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: as found in at least [0080]: the common Pbias lines 26 and Nbias 28 of both configuration memory cells 80-1 and 80-2 are biased at 0.8V. This sets the current level through both sides of the memory cells 80-1, 80-2 in this exemplary embodiment at about 50 μA during the operating mode. This current level prevents any disturb of the state of the memory cell during a read operation and limits the Vds across all word line select transistors 40 in the row to a maximum of 0.8V. (emphasis added)
Therefore, it would have been obvious to combine Martelloni as modified with McCollum to make the above modification.
As to claim 5, as found in the teachings of McCallum in at least FIG. 3, and as made obvious and well-known in the relevant art of semiconductor transistor operations: a bias level of the bias voltage is set to manage a drain-source voltage of a respective transistor via control of a gate-source voltage of the respective transistors (Consider transistor 38, it receives a bias voltage Nbias at its gate, whether Vgs-Vth of 38 is larger or smaller than Vds of itself, obviously manages a drain-source voltage of the “respective” transistor, in this case 38).
As to claim 7, at least McCollum obviates: wherein a respective transistor of one or both of the first inverter or the second inverter exhibits lower drain-source voltage tolerance than gate-drain voltage tolerance and gate-source voltage tolerance (As found in at least FIG. 1: transistor 38 receives at its gate a fixed bias Nbias voltage; any variation of Vgs and Vgd because the gate voltage is fixed can have a higher tolerance than a Vds tolerance, where Vd and Vs are not fixed).
As to claim 10, at least McCallum teaches comprising one or more impedance elements arranged between one or more of the first node or the second node and respective outputs of the first inverter and the second inverter (As found in at least FIG. 3: impedance element 82).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent/Publication No. 7504695 to Martelloni et al. (“Martelloni”) in view of U.S. Patent/Publication No. 7187597 to Trimberger (“Trimberger”), and further in view of US 20080155362 to Chang et al. (“Chang”) and US 20050276129 to Meihong et al. (Meihong”).
As to claim 6, at least Chang and Meihong, relevantly and complementarily teach wherein a totality of transistors of the first inverter and second inverter exhibit nonuniform voltage tolerance across their respective terminal nodes (As found in [0048] of Chang: The results of all of the measurements can then be evaluated for changing the design of the memory array or memory cells, for determining whether fabrication process has deviated exceedingly from tolerable norms or for determining operational ranges such as power supply voltage tolerances and access times; while Meihong teaches in at least [0007]: Because of variations in memory cell characteristics, variations in voltages applied, and variations in other parameters across an array, the biasing procedures used for programming and erasing operations in flash memory can result in nonuniform levels of charge stored in the cells distributed across the array).
Martelloni as modified Chang and Meihong are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory having cross-coupled inverters and operate at a supply level.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Martelloni as modified as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Chang and Meihong also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: variations in memory cell characteristics is not limited to transistors in memory cells, but includes all transistors and other devices found within the confines of a fabricated semiconductor device; process variation among a totality of transistors, resistors, capacitors, etc. include physical variations, electrical characteristic variations, and more. Chang and Meihong make this point exceedingly clear; moreover, it is well within the confines of well-known and well-understood semiconductor operations.
Therefore, it would have been obvious to combine Martelloni as modified with Chang and Meihong to make the above modification.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/ Primary Examiner, Art Unit 2827