Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 03/05/2025 and 08/05/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 8-9 and 16-19 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over US20220328408A1; Do et al.; (hereinafter “Do”).
Regarding Claim 1, Do teaches an integrated circuit device ([0004]), comprising:
a first cell (#MHC2, Figure 6) having a first height that is 1.5 times of a standard cell height ([0037], height of mixed height cell #MHC is 1.5 times standard/single height cell), wherein the first cell (#MHC2) comprises a first diffusion structure of a first diffusion type (#PR3, PMOS) aligned in a first direction and a second diffusion structure of a second diffusion type (#NR2-3, NMOS) aligned in the first direction; and
a second cell (#MHC1) having a second height that is one of 0.5 or 1.5 times the standard cell height ([0037]), wherein a top portion of the second cell (#MHC1) abuts a bottom portion of the first cell (#MHC2).
Regarding Claim 5, Do teaches the integrated circuit device as described in claim 1, wherein Do further teaches the first diffusion structure of the first diffusion type comprises a first plurality of nanosheets and/or nanowires and wherein the second diffusion structure of the second diffusion type comprises a second plurality of nanosheets and/or nanowires (Figure 12A, [0125-0128], NMOS #NR and PMOS #PR comprises stacked nanosheets).
Regarding Claim 8, Do teaches the integrated circuit device as described in claim 1, wherein Do further teaches a layout including the first cell and the second cell, wherein a bottom portion of the second cell abuts a top portion of a third cell having a third height that is one of an integer multiple of the standard cell height or an even integer multiple of 1.5 times the standard cell heigh (Figure 8, [0061-0065], various cells of single height, double height or mixed height can locate above or below the first and second cells).
Regarding Claim 9, Do teaches the integrated circuit device as described in claim 8, wherein Do further teaches at least a fourth 1.0H cell and at least a fifth 2.0H cell abutting left/right one or more of the first and second cells (Figure 8, [0061-0065], additional single height cells #SHC and double height cells #DHC can locate on the left/right side of the first and second mixed height cells #MHC).
Regarding Claim 16, Do teaches the integrated circuit device as described in claim 1, wherein Do further teaches a layout including a one or more third cells abutting left/right one or more fourth cells with no filler cells to transition between the one or more third cells and the one or more fourth cells (Figure 8, a plurality of adjacent various height cells #SHC-#MHC do not include filler cell for transition).
Regarding Claim 17, Do teaches the integrated circuit device as described in claim 1, wherein Do further teaches a layout further including one or more 0.5H cells or 2.5H cells, or any combination thereof (Figure 8, [0064-0066], cells #DMC1-2 have height of 0.5 times single height cell).
Regarding Claim 18, Do teaches the integrated circuit device as described in claim 1, wherein Do further teaches at least the first cell is implemented utilizing GAA FET, finFET, and/or CFET technologies ([0077] or [0135]).
Regarding Claim 19, Do teaches a method ([0004]), comprising:
forming a first cell (#MHC2, Figure 6) having a first height that is 1.5 times of a standard cell height ([0037], height of mixed height cell #MHC is 1.5 times standard/single height cell), wherein the first cell (#MHC2) comprises a first diffusion structure of a first diffusion type (#PR3, PMOS) aligned in a first direction and a second diffusion structure of a second diffusion type (#NR2-3, NMOS) aligned in the first direction; and
forming a second cell (#MHC1) having a second height that is one of 0.5 or 1.5 times the standard cell height ([0037]), wherein a top portion of the second cell (#MHC1) abuts a bottom portion of the first cell (#MHC2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Do in view of US20130313615A1; Tzeng et al.; (hereinafter “Tzeng”).
Regarding Claim 2, Do teaches the integrated circuit device as described in claim 1, wherein Do further teaches at least a portion of the first diffusion structure of the first diffusion type is positioned across a power rail (Figures 24-27, NMOS #NR1-2 or PMOS #PR1-2 dispose across power line).
Do does not explicitly teach a width of the first diffusion structure of the first diffusion type is greater than a width of the second diffusion structure of the second diffusion type.
However, Tzeng teaches an integrated circuit ([0009]), wherein a width of the first diffusion structure of the first diffusion type is greater than a width of the second diffusion structure of the second diffusion type (Figure 1, [0016], height of PMOS region can alternatively be greater or less than of NMOS region).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Do with the teaching of Tzeng as it would be a simple substitution of one known element (height of n-type/p-type region of Do) for another (height of n-type/p-type region of Tzeng) to obtain predictable results. See MPEP 2143(I)(B).
Regarding Claim 3, Do in view of Tzeng teaches the integrated circuit device as described in claim 2, wherein Do further teaches the first diffusion type comprises a P-type diffusion and the second diffusion type comprises an N-type diffusion (Figure 6, cell #MHC comprises NMOS #NR1-3 and PMOS #PR1-3).
Regarding Claim 4, Do in view of Tzeng teaches the integrated circuit device as described in claim 2, wherein Do further teaches the first diffusion type comprises an N-type diffusion and the second diffusion type comprises a P-type diffusion (Figure 6, cell #MHC comprises NMOS #NR1-3 and PMOS #PR1-3).
Claims 6-7 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Do in view of US20220237358A1; Yang et al.; (hereinafter “Yang”).
Regarding Claim 6, Do teaches the integrated circuit device as described in claim 1.
Do does not explicitly teach a width of the first diffusion structure of the first diffusion type comprises a nanosheet width (NSW) of approximately 65 nm.
However, Yang teaches an integrated circuit (Figure 2, [0033]), wherein a width of the first diffusion structure of the first diffusion type ([0038-0039] & [0047], n-type/p-type active regions of width W11/W12) comprises a nanosheet width (NSW) of approximately 65 nm ([0057]).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to have selected the overlapping range of Yang in order to optimize the functionality of the device. See MPEP §2144.05. Further, the specification contains no disclosure of either the critical nature of the specific claimed width or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990)
Regarding Claim 7, Do in view of Yang teaches the integrated circuit device as described in claim 6, wherein Do further teaches a width of the second diffusion structure comprises a nanosheet width (NSW) of approximately 35 nm (see rejection of claim 6, Yang, [0057], width W11/W12 is such as 35 nm).
Regarding Claim 20, Do teaches a fabrication of an apparatus ([0004]) comprising:
a first cell (#MHC2, Figure 6) having a first height that is 1.5 times of a standard cell height ([0037], height of mixed height cell #MHC is 1.5 times standard/single height cell), wherein the first cell (#MHC2) comprises a first diffusion structure of a first diffusion type (#PR3, PMOS) aligned in a first direction and a second diffusion structure of a second diffusion type (#NR2-3, NMOS) aligned in the first direction; and
a second cell (#MHC1) having a second height that is one of 0.5 or 1.5 times the standard cell height ([0037]), wherein a top portion of the second cell (#MHC1) abuts a bottom portion of the first cell (#MHC2).
Do does not explicitly teach a non-transitory computer-readable medium to store computer-readable code for fabrication of the apparatus.
However, Yang teaches a comparable integrated circuit (Figure 2), comprising a non-transitory computer-readable medium to store computer-readable code for fabrication of the apparatus ([0113], design layouts/program instructions can be stored in a non-transitory computer-readable storage medium).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Do with the teaching of Yang by known methods to yield predictable results (storing design circuit layouts/program instruction in a storage medium). See MPEP 2143(I)(A).
Claims 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over Do in view of US10497693B1; Huang et al.; (hereinafter “Huang”).
Regarding Claim 10, Do teaches the integrated circuit device as described in claim 9, wherein Do further teaches the first cell abuts left/right the fourth 1.0H cell (Figure 8, mixed height cells #MHC abuts left/right single height cells #SHC), and wherein the layout further comprises a first filler cell (#DMC1-2).
Do does not explicitly teach the first filler cell enabling a transition from one or more diffusion structures of the fourth 1.0H cell to one or more diffusion structures of the first cell.
However, Huang teaches an integrated circuit (col. 2, ln. 49-64), comprising a first filler cell enabling a transition from one or more diffusion structures of fourth 1.0H cell to one or more diffusion structures of first cell (Figures 2-3, col. 4, ln. 11-65, filler/transitional cells provide transition between various abutting cells).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Do with the teaching of Huang in order to provide transition between various cells and effectively utilize the area of semiconductor die according to Huang, col. 60-65.
Regarding Claim 11, Do in view of Huang teaches the integrated circuit device as described in claim 10, wherein Do further teaches the first filler cell comprises a 1.5H filler cell (see rejection of claim 10, Huang, col. 4, ln. 56-65, transitional cell has a height of 1.5 times standard height cell).
Regarding Claim 12, Do in view of Huang teaches the integrated circuit device as described in claim 11, wherein Do further teaches the second cell abuts left/right the at least the fifth 2.0H cell (Figure 8, mixed height cells #MHC abut left/right double height cells #DHC), and wherein the layout further comprises a second filler cell (#DMC1-2).
Do does not explicitly teach the second filler cell enabling a transition from one or more diffusion structures of the at least the fifth 2.0H cell to one or more diffusion structures of the second cell.
However, Huang teaches second filler cell enabling a transition from one or more diffusion structures of at least fifth 2.0H cell to one or more diffusion structures of second cell (Figures 2-3, col. 4, ln. 11-65, filler/transitional cells provide transition between various abutting cells).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Do with the teaching of Huang in order to provide transition between various cells and effectively utilize the area of semiconductor die according to Huang, col. 60-65.
Regarding Claim 13, Do in view of Huang teaches the integrated circuit device as described in claim 12.
Do does not teach the second filler cell comprises a 2.0H filler cell.
However, Huang teaches a second filler cell comprises a 2.0H filler cell (col. 5, ln. 4-38, an increase in usable fins in transitional cell increases drive strength of the cell).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Do with the teaching of Huang for reason set forth in rejection of claim 12.
Regarding Claim 14, Do in view of Huang teaches the integrated circuit device as described in claim 1, wherein Do further teaches a layout including a plurality of 1.0H cells abutting left/right a plurality of 1.5H cells (Figure 8, mixed height cells #MHC abut left/right single height cells #SHC), wherein the layout further comprises a plurality of 0.5H filler cells (#DMC1-2).
Do does not explicitly teach a plurality of 1.0H filler cells to enable transitions from a plurality of diffusion structures of the plurality of 1.0H cells to a plurality of diffusion structures of the plurality of 1.5H cells.
However, Huang teaches a plurality of 1.0H filler cells to enable transitions from a plurality of diffusion structures of the plurality of 1.0H cells to a plurality of diffusion structures of the plurality of 1.5H cells (col. 5, ln. 4-38, an increase in usable fins in transitional cell of various cell height, such 0.5 times standard cell or greater, increases the circuit performance).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Do with the teaching of Huang in order to provide transition between various cells and effectively utilize the area of semiconductor die according to Huang, col. 60-65.
Regarding Claim 15, Do teaches the integrated circuit device as described in claim 1, wherein Do further teaches a layout including a plurality of 1.0H cells abutting left/right a plurality of 1.5H cells (Figure 8, mixed height cells #MHC abut left/right single height cells #SHC).
Do does not explicitly teach a plurality of 1.5H filler cells to enable transitions from a plurality of diffusion structures of the plurality of 1.0H cells to a plurality of diffusion structures of the plurality of 1.5H cells.
However, Huang teaches a plurality of 1.5H filler cells to enable transitions from a plurality of diffusion structures of the plurality of 1.0H cells to a plurality of diffusion structures of the plurality of 1.5H cells (col. 4, ln. 56-65, transitional cells can have a height of 1.5 times standard height cells).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Do with the teaching of Huang in order to provide transition between various cells and effectively utilize the area of semiconductor die according to Huang, col. 60-65.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US20180150592A1 – Figures 1A-D, 3-8
US20180075182A1 – Figures 1, 3A-C
US20240186326A1 – Figures 4-7
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/TIEN TRAN/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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