DETAILED ACTION
This office action is in response to the application filed on 8/30/2024. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement
The present office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-20 are pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/20/2026 is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, 8-10 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nalla (US 2012/0074580).
With respect to Claim 1, Nalla shows (Fig. 2a-2j) all aspects of the current invention including a method of fabricating fan-out package, comprising:
forming packaging layers (206) on opposite sides of a supporting carrier (200), the packaging layers including one or more first packaging layers on a first side (top side) of the supporting carrier and one or more second package layers on a second side (bottom side) of the supporting carrier, the second side being opposite to the first side, the one or more first packaging layers including a first molded package layer (210), the one or more second packaging layers including a second molded package layer (210’), at least the first molded package layer embedding one or more semiconductor devices (die 206);
separating at least the one or more first packaging layers from the carrier board (see Fig 2h-2i)
With respect to Claim 2, Nalla shows (Fig. 2a-2j) wherein stress generated by forming the first molded package layer is about equal in magnitude as stress generated by forming the second molded package layer.
With respect to Claim 3, Nalla shows (Fig. 2a-2j) wherein the second molded package layer is about equal in thickness as the first molded package layer.
With respect to Claim 4, Nalla shows (Fig. 2a-2j) wherein forming packaging layers on opposite sides of the supporting carrier comprises:
forming the first bonding layer (202 top) on the first side and forming the second bonding layer (202 bottom) on the second side;
providing a semiconductor device (206), and attaching the passive face of the semiconductor device to one side surface of the first bonding layer facing away from the supporting carrier and/or one side surface of the second bonding layer facing away from the supporting carrier;
forming a molding layer (210); the molding layer wraps the semiconductor device and exposes the active surface of the semiconductor device, and the molding layer also covers one side surface of the first bonding layer facing away from the supporting carrier, and one side surface of the second bonding layer facing away from the supporting carrier, which is not covered by the semiconductor device;
forming a redistribution layer (layers 214,213,210’’) on a surface on one side of the molding layer facing away from the first bonding layer, and one side surface of the molding layer facing away from the second bonding layer; the redistribution layer is electrically connected to the active surface of the semiconductor device
With respect to Claim 6, Nalla shows (Fig. 2a-2j) wherein forming the molding layer comprises: forming the molding layer on a surface on one side of the first bonding layer facing away from the supporting carrier, and a surface on one side of the second bonding layer facing away from the supporting carrier; wherein, the molding layer covers the semiconductor device, and the molding layer also covers a surface of the first bonding layer facing away from the supporting carrier and a surface of the second bonding layer facing away from the supporting carrier. The side surface is not covered by the semiconductor device; and polishing the molding layer to expose the active surface of the semiconductor device
With respect to Claim 8, Nalla shows (Fig. 2a-2j) wherein attaching the passive surface of the semiconductor device to one side surface of the first bonding layer facing away from the supporting carrier and/or one side surface of the second bonding layer facing away from the supporting carrier comprises: attaching a passive surface of the semiconductor device to one side surface of the first bonding layer facing away from the supporting carrier and one side surface of the second bonding layer facing away from the supporting carrier; wherein, along the thickness direction of the molding layer, the projection of the semiconductor device attached to the first bonding layer overlaps with the projection of the semiconductor device attached to the second bonding layer
With respect to Claim 9, Nalla shows (Fig. 2a-2j) wherein the mentioned redistribution layer includes at least one metal layer (214) and at least one isolating layer (210’’), the metal layer corresponds to the isolating layer one by one; the redistribution layer is formed on one side surface of the molding layer facing away from the first bonding layer and one side surface of the molding layer facing away from the second bonding layer, and wherein: one side surface of the molding layer facing away from the first bonding layer, and one side surface of the molding layer facing away from the second bonding layer, are sequentially and alternately formed into one metal layer and one isolating layer, until one side surface of the molding layer facing away from the first bonding layer is formed into all metal layers and all isolating layers of the redistribution layer, and one side surface of the molding layer facing away from the second bonding layer is formed into all metal layers and all isolating layers of the redistribution layer.
With respect to Claim 10, Nalla shows (Fig. 2a-2j) after forming a redistribution layer on both a side surface of the molding layer facing away from the first bonding layer and a side surface of the molding layer facing away from the second bonding layer, the method further comprises: forming a connection structure (215) on one side surface of the redistribution layer, which is away from the semiconductor device; the connection structure is electrically connected to the redistribution layer and is used for connecting an external device
With respect to Claim 18, Nalla shows (Fig. 2a-2j) wherein forming packaging layers on opposite sides of the supporting carrier comprises: providing a supporting carrier; the supporting carrier comprises a first side and a second side which are oppositely arranged; forming a first bonding layer (202 top) on the first side of the supporting carrier and forming a second bonding layer (202 bottom) on the second side of the supporting carrier; forming a first redistribution layer (layers 214,213,210’’ on first side) on one side of the first bonding layer, which is away from the supporting carrier, and forming a second redistribution layer (layers 214’,213’’,210’’’ on second side) on one side of the second bonding layer, which is away from the supporting carrier; providing semiconductor devices (206,206’) and attaching an active face of the semiconductor devices to the first and/or second redistribution layers; and forming a molding layer (210,210’’); the molding layer embeds the semiconductor devices and also covers one side surface of the first bonding layer facing away from the supporting carrier, and one side surface of the second bonding layer facing away from the supporting carrier, which is not covered by the semiconductor device.
With respect to Claim 19, Nalla shows (Fig. 2a-2j) wherein the first redistribution layer comprises at least one metal layer and at least one insulator layer; the second redistribution layer comprises at least one metal layer and at least one insulator layer; the first redistribution layer is formed on one side of the first bonding layer which is away from the supporting carrier, and the second redistribution layer is formed on one side of the second bonding layer, which is away from the supporting carrier, and wherein forming the redistribution layer comprises: one side of the first bonding layer, which is away from the supporting carrier, and one side of the second bonding layer, which is away from the supporting carrier, alternately forming one metal layer and one insulator layer in sequence until one side of the first bonding layer, which is away from the supporting carrier, forming all metal layers and all insulator layers of the first redistribution layer, and one side of the second bonding layer, which is away from the supporting carrier, forming all metal layers and all insulator layers of the second redistribution layer
With respect to Claim 20, Nalla shows (Fig. 2a-2j) wherein attaching active faces of the semiconductor devices to the first and/or second redistribution layer comprises: attaching an active face of a first semiconductor device to a side surface of the first redistribution layer facing away from the first bonding layer and a stress balancing device or an active face of a second semiconductor device to a side surface of the second redistribution layer facing away from the second bonding layer; wherein, along the thickness direction of the support carrier, the projection of the first semiconductor device attached to the first redistribution layer overlaps with the projection of the stress balancing device or the second semiconductor device attached to the second redistribution layer
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Nalla (US 2012/0074580) in view of Chen (KR 2022/0102541A)
With respect to Claim 5, Nalla shows (Fig. 2a-2j) most aspects of the current invention. However, Nalla does not disclose wherein forming a first bonding layer on the first side and a second bonding layer on the second side comprises: forming the first bonding layer and the second bonding layer using a taping process or a coating process; and curing the first bonding layer and the second bonding layer.
On the other hand, and in the same field of endeavor, Chen teaches (Fig. 1-10) a method of fabricating fan-out package, comprising a supporting carrier (C1), the packaging layers including one or more first packaging layers on a first side (top side) of the supporting carrier, forming the first bonding layer (CF1) on the first side, wherein forming a first bonding layer on the first side using a taping process or a coating process; and curing the first bonding layer. Chen teaches a taping, or a coating process is well known in the semiconductor manufacturing art to use for forming bonding layers on carrier surfaces.
Additionally, although Chen does not teach forming the second bonding layer using a taping process or a coating process and curing the second bonding layer, the courts have held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced: the forming the second bonding layer using a taping process or a coating process and curing the second bonding layer claimed by the applicant is therefore only considered to be a duplication of the first bonding layer disclosed by Chen that a person having ordinary skill in the routing art would have been able to implement in the method of fabricating fan-out package using routine layout techniques based, among other things, bonding material, number of packaging layers, etc. (see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) )), since neither non-obvious nor unexpected results, i.e., results which are different in kind from the results of the prior art, will be obtained as the method for forming the first bonding layer, using taping process or a coating process is used, as already suggested by Chen.
Accordingly, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein forming a first bonding layer on the first side and a second bonding layer on the second side comprises: forming the first bonding layer and the second bonding layer using a taping process or a coating process; and curing the first bonding layer and the second bonding layer, in the device of Nalla, because it is known in the semiconductor manufacturing art to use a taping or a coating process for forming bonding layers on carrier surfaces, as taught by Chen, and applying a known method step for its conventional use would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
With respect to Claim 11, Nalla shows (Fig. 2a-2j) most aspects of the current invention including removing the supporting carrier. However, Nalla does not disclose removing the supporting carrier using thermal debonding, laser debonding or mechanical debonding.
On the other hand, and in the same field of endeavor, Chen teaches (Fig. 1-10) a method of fabricating fan-out package, comprising a supporting carrier (C1), the packaging layers including one or more first packaging layers on a first side (top side) of the supporting carrier, forming the first bonding layer (CF1) on the first side, providing semiconductor devices (100), and attaching the passive face of the semiconductor device to one side surface of the first bonding layer facing away from the supporting carrier, separating at least the one or more first packaging layers from the carrier board, wherein removing the supporting carrier comprises using thermal debonding, laser debonding or mechanical debonding. Chen teaches those suitable debonding methods are well known in the semiconductor manufacturing art to use for the removal of supporting carriers. (see Fig 7-8)
Accordingly, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have removing the supporting carrier using thermal debonding, laser debonding or mechanical debonding, in the device of Nalla, because it is known in the semiconductor manufacturing art to use those suitable debonding methods for the removal of supporting carriers, as taught by Chen, and applying a known method step for its conventional use would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
With respect to Claim 12, Chen teaches (Fig. 1-10) further comprising, after removing the supporting carrier: dicing the first packaging layers to obtain fan-out packages using at least one of dicing saw, dicing blades, laser grooving, and plasma cutting (see Fig 9-10)
Claims 7 and 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over Nalla (US 2012/0074580) in view of Lin (US 2014/0217597)
With respect to Claim 7, Nalla shows (Fig. 2a-2j) most aspects of the current invention. However, Nalla does not disclose wherein forming the molding layer comprise forming the molding layer using a compression molding or a transfer molding process.
On the other hand, and in the same field of endeavor, Lin teaches (Fig. 4a-4j) a method of fabricating fan-out package, comprising a supporting carrier (150), the packaging layers including one or more first packaging layers on a first side (top side) of the supporting carrier, forming the first bonding layer (152) on the first side, providing semiconductor devices (124), forming a molding layer (164); the molding layer embeds the semiconductor device and also covers one side surface of the first bonding surface facing away from the supporting carrier, wherein forming the molding layer comprise forming the molding layer using a compression molding or a transfer molding process (par 54). Lin teaches doing so allows the encapsulant to facilitates the subsequent formation of a fan-out build-up interconnect structure over encapsulant and semiconductor die (par 54).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of forming the molding layer comprise forming the molding layer using a compression molding or a transfer molding process in the device of Nalla,as taught by Lin, to allow the encapsulant to facilitate the subsequent formation of a fan-out build-up interconnect structure over encapsulant and semiconductor die.
With respect to Claim 13, Nalla shows (Fig. 2a-2j) wherein forming packaging layers on opposite sides of the supporting carrier comprises:
forming the first bonding layer (202 top) on the first side and forming the second bonding layer on the second side (202 bottom);
providing a semiconductor device (206), and attaching an active face of the semiconductor device to a surface of the first bonding layer facing away from the supporting carrier
forming a molding layer (210); the molding layer embeds the semiconductor device and also covers one side surface of the first bonding surface facing away from the supporting carrier and one side surface of the second bonding layer facing away from the supporting carrier, which is not covered by the semiconductor device
However, Nalla does not show providing a plurality of semiconductor devices and the molding layer embeds the semiconductor devices.
On the other hand, and in the same field of endeavor, Lin teaches (Fig. 4a-4j) a method of fabricating fan-out package, comprising a supporting carrier (150), the packaging layers including one or more first packaging layers on a first side (top side) of the supporting carrier, forming the first bonding layer (152) on the first side, providing semiconductor devices (124), forming a molding layer (164); the molding layer embeds the semiconductor devices and also covers one side surface of the first bonding surface facing away from the supporting carrier (par 54). Lin teaches doing so allows the encapsulant to facilitates the subsequent formation of a fan-out build-up interconnect structure over encapsulant and semiconductor die (par 54).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of providing a plurality of semiconductor devices, and the molding layer embeds the semiconductor devices in the device of Nalla, as taught by Lin, to allow the encapsulant to facilitate the subsequent formation of a fan-out build-up interconnect structure over encapsulant and semiconductor die.
With respect to Claim 14, Nalla shows (Fig. 2a-2j) after attaching the active face of the semiconductor device to the side surface of the first bonding layer facing away from the supporting carrier, the method further comprises: attaching stress balancing device (206’) to the surface of one side of the second bonding layer away from the supporting carrier; and the projection of the semiconductor devices is overlapped with the projection of the stresses balance device along the thickness direction of the supporting carrier.
With respect to Claim 15, Lin teaches (Fig. 4a-4j) further comprising: forming grooves on in a surface of one side of the molding layer, which is away from the first bonding layer, to release stress (see Fig 4h)
With respect to Claim 16, Lin teaches (Fig. 4a-4j) wherein forming grooves in the surface of the molding layer facing away from the first bonding layer comprises: forming each grooves between two adjacent semiconductor devices (see Fig 4h)
With respect to Claim 17, Lin teaches (Fig. 4a-4j) wherein along the thickness direction of the molding layer, the depth of each groove is smaller than or equal to 1/2 of the thickness of the molding layer.
Claim Objections
Claim 6 is objected to because of the following informalities: The claim seems to have some language that needs correction and rewording. Appropriate correction is required.
Conclusion
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/Q. B./
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
