Technology area: Semiconductors, Circuits & Optics
5 pending office actions • 3 art units • 4 examiners • 0 of 5 (0%) have an AI response strategy ready • 1 patents granted in the last 365 days
Yibu Semiconductor Co. Ltd. has 5 pending office actions within the Semiconductors, Circuits & Optics technology area. These actions are handled by 4 distinct examiners, indicating that at least one examiner is managing more than one action. The data shows that 3 distinct art units are involved in the prosecution of these filings. This involvement of 3 distinct art units means the portfolio is subject to the review of multiple technical divisions within the patent office.
The busiest examiner, STARK, JARRETT J, is responsible for 2 busiest examiner pending office actions. Since STARK, JARRETT J manages 2 of the 5 pending office actions, this examiner has a larger relative impact on the portfolio than the other 4 distinct examiners. Practitioners should note that while the 5 pending office actions are spread across 3 distinct art units, the concentration of 2 actions with a single examiner may allow for consistency in prosecution strategy. The 4 distinct examiners must be managed across the 3 distinct art units to ensure results in the Semiconductors, Circuits & Optics area.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §102 only | 1 (20%) |
| Multi-statute (no §101) | 4 (80%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| STARK, JARRETT J | 2 | 70.4% | +11.0% |
| BRASFIELD, QUINTON A | 1 | 72.2% | +17.2% |
| KARIMY, TIMOR | 1 | 82.2% | +9.2% |
| AU, BAC H | 1 | 81.1% | +10.9% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 1 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18401325 | STACKED PACKAGE, METHOD OF MAKING AND ELECTRONIC DEVICE INCLUDING THE STACKED PACKAGE | KARIMY, TIMOR | — |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 4 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18822052 | METHOD FOR FABRICATING FAN-OUT PACKAGE | BRASFIELD, QUINTON A | — |
| 18754081 | CHIP STACK AND FABRICATION METHOD | STARK, JARRETT J | — |
| 18664273 | MULTI-CHIP PACKAGE AND METHOD OF MAKING | STARK, JARRETT J | — |
| 18401329 | FAN-OUT STACKED PACKAGE, METHOD OF MAKING AND ELECTRONIC DEVICE INCLUDING THE STACKED PACKAGE | AU, BAC H | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 4 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18822052 | METHOD FOR FABRICATING FAN-OUT PACKAGE | BRASFIELD, QUINTON A | — |
| 18754081 | CHIP STACK AND FABRICATION METHOD | STARK, JARRETT J | — |
| 18664273 | MULTI-CHIP PACKAGE AND METHOD OF MAKING | STARK, JARRETT J | — |
| 18401329 | FAN-OUT STACKED PACKAGE, METHOD OF MAKING AND ELECTRONIC DEVICE INCLUDING THE STACKED PACKAGE | AU, BAC H | — |
| Art Unit | Apps |
|---|---|
| 2898 | 3 |
| 2814 | 1 |
| 2818 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 18822052 | METHOD FOR FABRICATING FAN-OUT PACKAGE | BRASFIELD, QUINTON A | 2814 | §102§103 | Non-Final OA | — | Pending | Aug 30, 2024 |
| 18754081 | CHIP STACK AND FABRICATION METHOD | STARK, JARRETT J | 2898 | §102§103 | Non-Final OA | — | Pending | Jun 25, 2024 |
| 18664273 | MULTI-CHIP PACKAGE AND METHOD OF MAKING | STARK, JARRETT J | 2898 | §102§103 | Non-Final OA | — | Pending | May 14, 2024 |
| 18401325 | STACKED PACKAGE, METHOD OF MAKING AND ELECTRONIC DEVICE INCLUDING THE STACKED PACKAGE | KARIMY, TIMOR | 2818 | §102 | Non-Final OA | — | Pending | Dec 29, 2023 |
| 18401329 | FAN-OUT STACKED PACKAGE, METHOD OF MAKING AND ELECTRONIC DEVICE INCLUDING THE STACKED PACKAGE | AU, BAC H | 2898 | §102§103 | Non-Final OA | — | Pending | Dec 29, 2023 |
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Start Free TrialYibu Semiconductor Co. Ltd. has 5 pending office actions as of October 2026, spread across 3 art units and 4 examiners.
Jarrett J Stark has the most, with 2 of Yibu Semiconductor Co. Ltd.'s pending office actions.
Mostly Semiconductors, Circuits & Optics (USPTO Tech Center 2800), based on where its pending office actions are examined.
