DETAILED ACTION
This Office Action is in response to Applicant’s application 18/822,185 filed on August 31, 2024 in which claims 1 to 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings submitted on August 31, 2024 have been reviewed and accepted by the Examiner.
Information Disclosure Statement
The Information Disclosure Statements (IDS), filed on December 2, 2024 and June 25, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein has been considered by the Examiner.
Priority
Receipt is acknowledged of paper submitted under 35 U.S.C. 119(a)-(d) or under 35 U.S.C. 120, 121, 365(c), or 386(c) which has been placed of record in the file.
Notation
References to patents will be in the form of [C:L] where C is the column number and L is the line number. References to pre-grant patent publications will be to the paragraph number in the form of [xxxx].
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-9 of U.S. Patent No. 12,113,073 (‘073). Although the claims at issue are not identical, they are not patentably distinct from each other as discussed below.
Table 1 – Comparison of Pending Claims to ‘073 Claims
Pending Claim
‘073 Patent
1. An array substrate comprising:
a base substrate; and a thin film transistor disposed on the base substrate, wherein
the thin film transistor comprises a first gate, a first semiconductor layer, a second semiconductor layer, a second gate, a source electrode and a drain electrode that are sequentially disposed on the base substrate;
wherein a length of the first semiconductor layer is greater than a length of the second semiconductor layer, and
an area of the first semiconductor layer covered by the second semiconductor layer is a conductive channel of the thin film transistor.
1. An array substrate, comprising
a base substrate and a thin film transistor disposed on the base substrate, and
the thin film transistor comprises a first gate, a first semiconductor layer, a second semiconductor layer, a second gate, a source electrode and a drain electrode which are sequentially disposed on the base substrate,
wherein a conductive channel of the thin film transistor is formed on a contact surface of the first semiconductor layer and the second semiconductor layer; and
wherein a carrier concentration of the first semiconductor layer is greater than a carrier concentration of the second semiconductor layer.
4. The array substrate according to claim 1, wherein both the first gate and the second gate are connected to a negative voltage.
5. The array substrate according to claim 4, further comprising: a first gate insulating layer, covering the first gate and the base substrate, and the first semiconductor layer is disposed on the first insulating layer and the second semiconductor layer is disposed on the first semiconductor layer, and an orthographic projection of the second semiconductor layer on the base substrate is within an orthographic projection of the first semiconductor layer on the base substrate;
a second gate insulating layer, covering the second semiconductor layer, and the second gate is disposed on the second insulating layer, and the second gate is disposed corresponding to the conductive channel;
an interlayer insulating layer, covering the second gate and the first gate insulating layer, and the source electrode and the drain electrode are disposed on the interlayer insulating layer, and a plurality of first via holes are disposed in the interlayer insulating layer;
wherein the first semiconductor layers located on both sides of the conductive channel form a source region and a drain region of the thin film transistor, and the source electrode and the drain electrode are respectively connected to the source region and the drain region through the corresponding first via holes.
6. The array substrate according to claim 5, wherein the thin film transistor further comprises a bridge electrode, and the second gate is electrically connected to the first gate through the bridge electrode.
9. The array substrate according to claim 5, wherein a length of the second semiconductor layer is smaller than a length of the first semiconductor layer.
2. The array substrate according to claim 1,
wherein a carrier concentration of the first semiconductor layer is greater than a carrier concentration of the second semiconductor layer.
From claim 1
wherein a carrier concentration of the first semiconductor layer is greater than a carrier concentration of the second semiconductor layer.
3. The array substrate according to claim 1, wherein materials of the first semiconductor layer and the second semiconductor layer comprise indium gallium zinc oxide.
2. The array substrate according to claim 1, wherein materials of the first semiconductor layer and the second semiconductor layer comprise indium gallium zinc oxide.
4. The array substrate according to claim 3, wherein a content of gallium in the first semiconductor layer is less than a content of gallium in the second semiconductor layer.
3. The array substrate according to claim 2, wherein a content of gallium in the first semiconductor layer is less than a content of gallium in the second semiconductor layer.
5. The array substrate according to claim 1, wherein both of the first gate and the second gate are connected to a negative voltage.
4. The array substrate according to claim 1, wherein both the first gate and the second gate are connected to a negative voltage
6. The array substrate according to claim 1, further comprising:
a first gate insulating layer covering the first gate and the base substrate, wherein the first semiconductor layer is disposed on the first insulating layer, the second semiconductor layer is disposed on the first semiconductor layer, and an orthographic projection of the second semiconductor layer on the base substrate is within an orthographic projection of the first semiconductor layer on the base substrate;
a second gate insulating layer covering the second semiconductor layer, wherein the second gate is disposed on the second insulating layer, and the second gate is disposed corresponding to the conductive channel; and
an interlayer insulating layer covering the second gate and the first gate insulating layer, wherein the source electrode and the drain electrode are disposed on the interlayer insulating layer, and a plurality of first via holes are disposed in the interlayer insulating layer;
wherein the first semiconductor layers located on both sides of the conductive channel form a source region and a drain region of the thin film transistor, and the source electrode and the drain electrode are respectively connected to the source region and the drain region through the corresponding first via holes.
5. The array substrate according to claim 4, further comprising:
a first gate insulating layer, covering the first gate and the base substrate, and the first semiconductor layer is disposed on the first insulating layer and the second semiconductor layer is disposed on the first semiconductor layer, and an orthographic projection of the second semiconductor layer on the base substrate is within an orthographic projection of the first semiconductor layer on the base substrate;
a second gate insulating layer, covering the second semiconductor layer, and the second gate is disposed on the second insulating layer, and the second gate is disposed corresponding to the conductive channel;
an interlayer insulating layer, covering the second gate and the first gate insulating layer, and the source electrode and the drain electrode are disposed on the interlayer insulating layer, and a plurality of first via holes are disposed in the interlayer insulating layer;
wherein the first semiconductor layers located on both sides of the conductive channel form a source region and a drain region of the thin film transistor, and the source electrode and the drain electrode are respectively connected to the source region and the drain region through the corresponding first via holes.
7. The array substrate according to claim 6, wherein the thin film transistor further comprises a bridge electrode, and the second gate is electrically connected to the first gate through the bridge electrode.
6. The array substrate according to claim 5, wherein the thin film transistor further comprises a bridge electrode, and the second gate is electrically connected to the first gate through the bridge electrode.
8. The array substrate according to claim 7, wherein the bridge electrode and the source electrode are disposed in a same layer, the interlayer insulating layer is further disposed with a second via hole and a third via hole, and the bridge electrode is connected to the second gate through the second via hole, and is connected to the first gate through the third via hole.
7. The array substrate according to claim 6, wherein the bridge electrode and the source electrode are disposed in a same layer, and the interlayer insulating layer is further disposed with a second via hole and a third via hole, and the bridge electrode is connected to the second gate through the second via hole, and is connected to the first gate through the third via hole.
9. The array substrate according to claim 1, wherein the orthographic projection of the first semiconductor layer on the base substrate is within an orthographic projection of the first gate on the base substrate.
8. The array substrate according to claim 5, wherein the orthographic projection of the first semiconductor layer on the base substrate is within an orthographic projection of the first gate on the base substrate.
10. The array substrate according to claim 1, wherein an area of the first semiconductor layer not covered by the second semiconductor layer comprises a source region and a drain region of the thin film transistor, and the source region and the drain region are disposed at opposite sides of the conductive channel, respectively.
Obvious to try
11. A display panel comprising:
an array substrate comprising a base substrate and a thin film transistor disposed on the base substrate, wherein
the thin film transistor comprises a first gate, a first semiconductor layer, a second semiconductor layer, a second gate, a source electrode and a drain electrode that are sequentially disposed on the base substrate;
wherein a length of the first semiconductor layer is greater than a length of the second semiconductor layer, and
an area of the first semiconductor layer covered by the second semiconductor layer is a conductive channel of the thin film transistor.
1. An array substrate, comprising
a base substrate and a thin film transistor disposed on the base substrate, and
the thin film transistor comprises a first gate, a first semiconductor layer, a second semiconductor layer, a second gate, a source electrode and a drain electrode which are sequentially disposed on the base substrate,
wherein a conductive channel of the thin film transistor is formed on a contact surface of the first semiconductor layer and the second semiconductor layer; and
wherein a carrier concentration of the first semiconductor layer is greater than a carrier concentration of the second semiconductor layer.
4. The array substrate according to claim 1, wherein both the first gate and the second gate are connected to a negative voltage.
5. The array substrate according to claim 4, further comprising: a first gate insulating layer, covering the first gate and the base substrate, and the first semiconductor layer is disposed on the first insulating layer and the second semiconductor layer is disposed on the first semiconductor layer, and an orthographic projection of the second semiconductor layer on the base substrate is within an orthographic projection of the first semiconductor layer on the base substrate;
a second gate insulating layer, covering the second semiconductor layer, and the second gate is disposed on the second insulating layer, and the second gate is disposed corresponding to the conductive channel;
an interlayer insulating layer, covering the second gate and the first gate insulating layer, and the source electrode and the drain electrode are disposed on the interlayer insulating layer, and a plurality of first via holes are disposed in the interlayer insulating layer;
wherein the first semiconductor layers located on both sides of the conductive channel form a source region and a drain region of the thin film transistor, and the source electrode and the drain electrode are respectively connected to the source region and the drain region through the corresponding first via holes.
6. The array substrate according to claim 5, wherein the thin film transistor further comprises a bridge electrode, and the second gate is electrically connected to the first gate through the bridge electrode.
9. The array substrate according to claim 5, wherein a length of the second semiconductor layer is smaller than a length of the first semiconductor layer.
12. The display panel according to claim 11, wherein a carrier concentration of the first semiconductor layer is greater than a carrier concentration of the second semiconductor layer.
From claim 1
wherein a carrier concentration of the first semiconductor layer is greater than a carrier concentration of the second semiconductor layer.
13. The display panel according to claim 11, wherein materials of the first semiconductor layer and the second semiconductor layer comprise indium gallium zinc oxide.
2. The array substrate according to claim 1, wherein materials of the first semiconductor layer and the second semiconductor layer comprise indium gallium zinc oxide.
14. The display panel according to claim 13, wherein a content of gallium in the first semiconductor layer is less than a content of gallium in the second semiconductor layer.
3. The array substrate according to claim 2, wherein a content of gallium in the first semiconductor layer is less than a content of gallium in the second semiconductor layer.
15. The display panel according to claim 11, wherein both of the first gate and the second gate are connected to a negative voltage.
4. The array substrate according to claim 1, wherein both the first gate and the second gate are connected to a negative voltage
16. The display panel according to claim 11, wherein an area of the first semiconductor layer not covered by the second semiconductor layer comprises a source region and a drain region of the thin film transistor, and the source region and the drain region are disposed at opposite sides of the conductive channel, respectively.
Obvious to try
Regarding claim 1 and referring to Table 1, Examiner notes that claim 1 of the ‘073 patent provides that the first and second semiconductor layers form a channel and so teaches and/or suggests an area of the first semiconductor layer covered by the second semiconductor layer is a conductive channel of the thin film transistor because each is sequentially disposed. Claim 9 which depends indirectly on claim 1 provides that a length of the second semiconductor layer is smaller than a length of the first semiconductor layer which also describes the condition a length of the first semiconductor layer is greater than a length of the second semiconductor layer. Thus the subject matter of pending claim 1 is taught and suggested by claim 9 of the ‘073 patent.
Regarding claim 2, claim 1 of the ‘073 patent teaches this subject matter.
Regarding claim 3, claim 2 of the ‘073 patent teaches this subject matter is a useful modification of claim 1 of the ‘073 patent.
Regarding claim 4, claim 3 of the ‘073 patent teaches this subject matter is a useful modification of claim 1 of the ‘073 patent.
Regarding claim 5, claim 4 of the ‘073 patent, on which claim 9 depends, teaches this subject matter.
Regarding claim 6, claim 5 of the ‘073 patent, on which claim 9 depends, teaches this subject matter.
Regarding claim 7, claim 6 of the ‘073 patent, on which claim 9 depends, teaches this subject matter.
Regarding claim 8, claim 7 of the ‘073 patent, teaches this subject matter as an alternative to claim 5 and so is within the scope of claim 9.
Regarding claim 9, claim 5 of the ‘073 patent, teaches this subject matter as an alternative to claim 5 and so is within the scope of claim 9.
Regarding claim 10 which depends upon claim 1, Examiner notes source/drain regions on opposite sides of a channel and placing the source drain regions in the first layer not covered by the second layer is one of a finite number of ways to place the source drain regions on the first layer each of which an artisan could try with a reasonable chance of success. Accordingly, it would have been obvious to an artisan to try the device of claim 1 wherein an area of the first semiconductor layer not covered by the second semiconductor layer comprises a source region and a drain region of the thin film transistor, and the source region and the drain region are disposed at opposite sides of the conductive channel, respectively. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 421 (2007).
Regarding claim 11 and referring to Table 1, Examiner notes that claim 1 of the ‘073 patent provides that the first and second semiconductor layers form a channel and so teaches and/or suggests an area of the first semiconductor layer covered by the second semiconductor layer is a conductive channel of the thin film transistor because they are sequentially disposed. Claim 9 which depends indirectly on claim 1 provides that a length of the second semiconductor layer is smaller than a length of the first semiconductor layer which also describes the condition a length of the first semiconductor layer is greater than a length of the second semiconductor layer. Thus, the subject matter of pending claim 11 is taught and suggested by claim 9 of the ‘073 patent.
Regarding claim 12, claim 1 of the ‘073 patent teaches this subject matter.
Regarding claim 13, claim 2 of the ‘073 patent teaches this subject matter is a useful modification of claim 1 of the ‘073 patent.
Regarding claim 14, claim 3 of the ‘073 patent teaches this subject matter is a useful modification of claim 1 of the ‘073 patent.
Regarding claim 15, claim 4 of the ‘073 patent, on which claim 9 depends, teaches this subject matter.
Regarding claim 16 which depends upon claim 11, Examiner notes source/drain regions on opposite sides of a channel and placing the source drain regions in the first layer not covered by the second layer is one of a finite number of ways to place the source drain regions on the first layer each of which an artisan could try with a reasonable chance of success. Accordingly, it would have been obvious to an artisan to try the device of claim 11 wherein an area of the first semiconductor layer not covered by the second semiconductor layer comprises a source region and a drain region of the thin film transistor, and the source region and the drain region are disposed at opposite sides of the conductive channel, respectively. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 421 (2007).
Allowable Subject Matter
Claims 17-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 17, the prior art fails to disclose the method of claim 15 wherein a length of the first semiconductor layer is greater than a length of the second semiconductor layer.
Claims 18-20 depend directly or indirectly on claim 15 and are allowable on that basis.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is listed on the notice of references cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joe Schoenholtz whose telephone number is (571)270-5475. The examiner can normally be reached M-Thur 7 AM to 7 PM PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ms. Yara Green can be reached at (571) 272-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.E. Schoenholtz/Primary Examiner, Art Unit 2893
Prosecution Insights