DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 3/18/2026 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhai et al. (US 20200365078), in view of Kim et al. (US 20210210003).
As to claim 1, Zhai teaches an electronic device [fig. 14 & para. 121] comprising:
a processor [fig. 14 & para. 121] configured to provide input image data; and
a display device (display device) [abstract & fig. 14 & para. 120-121] configured to receive the input image data from the processor, and to display an image based on the input image data, the display device comprising a plurality of pixels (a plurality of pixels utilizing same pixel type utilzing light emitting element 500) [abstract & para. 117 & 122], each of the plurality of pixels comprising:
a light emitting element (light emitting element 500) [fig. 11];
a pulse width modulation (PWM) circuit (PWM circuit comprising second transistor t2, third transistor t3, fourth transistor t4, fifth transistor t5, & sixth transistor t6) [fig. 11] configured to control an emission time of the light emitting element based on a PWM data voltage (first data voltage d1) [fig. 11], a sweep voltage (pulse width control voltage sweep) [figs. 11-12 & para. 107-109 & 113-116], and a reference voltage (turn-off signal voff) [figs. 11-12 & para. 109-110 & 116];
a constant current generation (CCG) circuit (CCG circuit comprising first transistor t1, seventh transistor t7, eighth transistor t8, ninth transistor t9, drive transistor t0, twelfth transistor t12, thirteenth transistor t13) [fig. 11] configured to provide a constant driving current to the light emitting element based on a constant current data voltage (second data voltage d2) [fig. 11] and a power supply voltage (first voltage v1) [fig. 11]; and
a connection switch (eleventh transistor t11) [fig. 11] configured to connect the PWM circuit to the CCG circuit,
wherein the light emitting elements of the plurality of pixels substantially simultaneously start emitting light at a start time point of an emission period (light emitting control period s103) [figs. 11-12 & para. 113],
wherein, in each of the plurality of pixels, the PWM circuit transfers the reference voltage to the CCG circuit through the connection switch at a time point corresponding to a voltage level of the PWM data voltage (light emitting turn-off period s104) [figs. 11-12 & para. 110 & 116], and the CCG circuit causes the light emitting element to stop emitting light in response to the reference voltage (light emitting turn-off period s104) [figs. 11-12 & para. 110 & 116], and
wherein the reference voltage is applied to the PWM circuit (turn-off signal voff) [figs. 11-12 & para. 109-110 & 116], the power supply voltage is applied to the CCG circuit (first voltage v1) [fig. 11], and
wherein the constant current data voltage is provided to the plurality of pixels (second data voltage d2) [fig. 11].
Zhai does not explicitly teach wherein the reference voltage is higher than or equal to the power supply voltage.
However, there are only three options regarding the relationship between the reference voltage and the power supply voltage.
The reference voltage is higher than the power supply voltage.
The reference voltage is lower than the power supply voltage.
The reference voltage is equal to the power supply voltage.
The group of approaches address the need to provide a reference voltage to turn off a PMOS transistor and a power supply voltage to energize a light emitting element with a reasonable level of success.
Therefore it would have been obvious to try to modify the relationship between the reference voltage and the power supply voltage of the display device of the electronic device of Zhai, such that the reference voltage is higher than or equal to the power supply voltage, as is commonly known in the art, since there are a finite number of identified, predictable potential solutions to the recognized need (as discussed above) and one of ordinary skill in the art could have pursued the known potential solutions with a reasonable expectation of success.
Zhai does not explicitly teach wherein the constant current data voltage is provided to the plurality of pixels and is the same among the plurality of pixels.
Kim teaches the concept of an electronic device [abstract], wherein a constant current data voltage is provided to a plurality of pixels and is the same among the plurality of pixels (plurality of same pixel type receive same constant current generator voltage) [fig. 12 & para. 234].
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention modify the constant current data utilized with the constant current generation circuit of the display device of the electronic device of Zhai, such that the constant current data voltage is provided to the plurality of pixels and is the same among the plurality of pixels, as taught by Kim, to improve image quality by optimizing applied constant current generator voltage to characteristics of the plurality of pixels of the display device of the electronic device of Zhai, as one of ordinary skill in the art would appreciate.
As to claim 2, Zhai as modified by Kim teaches the electronic device of claim 1, wherein a voltage level of the PWM data voltage for each of the plurality of pixels is determined according to image data for each of the plurality of pixels [Zhai: figs. 11-12 & para. 113-115 & 72].
As to claim 3, Zhai as modified by Kim teaches the electronic device of claim 1, wherein the sweep voltage is provided to the plurality of pixels and is the same among the plurality of pixels, and
wherein the sweep voltage gradually decreases in the emission period (pulse width control voltage sweep) [Zhai: figs. 11-12 & para. 107-109 & 113-116].
As to claim 4, Zhai as modified by Kim teaches the electronic device of claim 1, wherein the PWM circuit comprises:
a first transistor (fifth transistor t5) [Zhai: fig. 11] including a gate, a first terminal, and a second terminal;
a second transistor (third transistor t3) [Zhai: fig. 11] including a gate configured to receive a first writing signal (control signal (s2’)s3) [Zhai: figs. 11-12], a first terminal connected to a first data line (first data voltage d1) [Zhai: fig. 11], and a second terminal connected to the first terminal of the first transistor (fifth transistor t5) [Zhai: fig. 11];
a third transistor (fourth transistor t4) [Zhai: fig. 11] including a gate configured to receive a first emission signal (fourth control signal s4) [Zhai: figs. 11-12], a first terminal connected to a line associated with transferring the reference voltage (turn-off signal voff) [Zhai: figs. 11-12 & para. 109-110 & 116], and a second terminal connected to the first terminal of the first transistor (fifth transistor t5) [Zhai: fig. 11];
a fourth transistor (sixth transistor t6) [Zhai: fig. 11] including a gate configured to receive a third writing signal (control signal s5(s2’)) [Zhai: figs. 11-12], a first terminal connected to the second terminal of the first transistor (fifth transistor t5) [Zhai: fig. 11], and a second terminal connected to the gate of the first transistor (fifth transistor t5) [Zhai: fig. 11]; and
a first capacitor (first capacitor c1) [Zhai: fig. 11] including a first electrode connected to a line associated with transferring the sweep voltage (pulse width control voltage sweep) [Zhai: figs. 11-12 & para. 107-109 & 113-116] and a second electrode connected to the gate of the first transistor (fifth transistor t5) [Zhai: fig. 11].
Allowable Subject Matter
Claims 5-13, 15, & 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 20 is allowed.
The following is an examiner’s statement of reasons for allowance:
Zhai et al. (US 20200365078), teaches an electronic device [fig. 14 & para. 121] comprising:
a processor [fig. 14 & para. 121] configured to provide input image data; and
a display device (display device) [abstract & fig. 14 & para. 120-121] configured to receive the input image data from the processor, and to display an image based on the input image data, the display device comprising a plurality of pixels [abstract & para. 117 & 122], each of the plurality of pixels comprising:
a light emitting element (light emitting element 500) [fig. 11];
a first transistor (fifth transistor t5) [fig. 11] including a gate, a first terminal, and a second terminal;
a second transistor (third transistor t3) [fig. 11] including a gate configured to receive a first writing signal (control signal (s2’)s3) [figs. 11-12], a first terminal connected to a first data line (first data voltage d1) [fig. 11], and a second terminal connected to the first terminal of the first transistor (fifth transistor t5) [fig. 11];
a third transistor (fourth transistor t4) [fig. 11] including a gate configured to receive a first emission signal (fourth control signal s4) [figs. 11-12], a first terminal connected to a line associated with transferring a reference voltage (turn-off signal voff) [figs. 11-12 & para. 109-110 & 116], and a second terminal connected to the first terminal of the first transistor (fifth transistor t5) [fig. 11];
a fourth transistor (sixth transistor t6) [fig. 11] including a gate configured to receive a third writing signal (control signal s5(s2’)) [figs. 11-12], a first terminal connected to the second terminal of the first transistor (fifth transistor t5) [fig. 11], and a second terminal connected to the gate of the first transistor (fifth transistor t5) [fig. 11];
a first capacitor (first capacitor c1) [fig. 11] including a first electrode connected to a line associated with transferring a sweep voltage (pulse width control voltage sweep) [figs. 11-12 & para. 107-109 & 113-116] and a second electrode connected to the gate of the first transistor (fifth transistor t5) [fig. 11];
a fifth transistor (second transistor t2) [fig. 11] including a gate configured to receive a first initialization signal (second reference voltage vref2) [fig. 11], a first terminal connected to a line associated with transferring an initialization voltage (second reference voltage vref2) [fig. 11], and a second terminal connected to the gate of the first transistor (fifth transistor t5) [fig. 11];
a sixth transistor (first transistor t1) [fig. 11] including a gate configured to receive a second initialization signal (first reference voltage vref1) [fig. 11], a first terminal connected to a line associated with transferring an anode initialization voltage (terminal supplying first reference voltage vref1) [fig. 11], and a second terminal connected to an anode of the light emitting element (light emitting element 500) [fig. 11];
a seventh transistor (drive transistor t0) [fig. 11] including a gate, a first terminal, and a second terminal;
an eighth transistor (ninth transistor t9) [fig. 11] including a gate configured to receive a second writing signal (control signal s8(s2’)) [figs. 11-12], a first terminal connected to a second data line (second data voltage d2) [fig. 11], and a second terminal connected to the first terminal of the seventh transistor (drive transistor t0) [fig. 11];
a ninth transistor (twelfth transistor t12) [fig. 11] including a gate configured to receive a third emission signal (third light emitting control signal k3) [figs. 11-12], a first terminal connected to a line associated with transferring a power supply voltage (first voltage v1) [fig. 11], and a second terminal connected to the first terminal of the seventh transistor (drive transistor t0) [fig. 11];
a tenth transistor (eighth transistor t8) [fig. 11] including a gate configured to receive a fourth writing signal (control signal s7(s2’)) [fig. 11], a first terminal connected to the second terminal of the seventh transistor (drive transistor t0) [fig. 11], and a second terminal connected to the gate of the seventh transistor (drive transistor t0) [fig. 11];
a second capacitor (second capacitor c2) [fig. 11] including a first electrode connected to the line associated with transferring the power supply voltage and a second electrode connected to the gate of the seventh transistor (drive transistor t0) [fig. 11];
an eleventh transistor (thirteenth transistor t13) [fig. 11] including a gate configured to receive the third emission signal (third light emitting control signal k3) [figs. 11-12], a first terminal connected to the second terminal of the seventh transistor (drive transistor t0) [fig. 11], and a second terminal connected to the anode of the light emitting element (light emitting element 500) [fig. 11]; and
a twelfth transistor (eleventh transistor t11) [fig. 11] including a gate configured to receive a second emission signal (second light emitting control signal k2) [fig. 11 & para. 104-108 & 110-115], a first terminal connected to the second terminal of the first transistor (fifth transistor t5) [fig. 11], and a second terminal connected to the gate of the seventh transistor (drive transistor t0) [fig. 11].
As to claim 20, the prior art fails to teach or suggest, “a display device configured to receive the input image data from the processor, and to display an image based on the input image data, the display device comprising a plurality of pixels, each of the plurality of pixels comprising:
a light emitting element;
a first transistor including a gate, a first terminal, and a second terminal;
a second transistor including a gate configured to receive a first writing signal, a first terminal connected to a first data line, and a second terminal connected to the first terminal of the first transistor;
a third transistor including a gate configured to receive a first emission signal, a first terminal connected to a line associated with transferring a reference voltage, and a second terminal connected to the first terminal of the first transistor;
a fourth transistor including a gate configured to receive a third writing signal, a first terminal connected to the second terminal of the first transistor, and a second terminal connected to the gate of the first transistor;
a first capacitor including a first electrode connected to a line associated with transferring a sweep voltage and a second electrode connected to the gate of the first transistor;
a fifth transistor including a gate configured to receive a first initialization signal, a first terminal connected to a line associated with transferring an initialization voltage, and a second terminal connected to the gate of the first transistor;
a sixth transistor including a gate configured to receive a second initialization signal, a first terminal connected to a line associated with transferring an anode initialization voltage, and a second terminal connected to an anode of the light emitting element;
a seventh transistor including a gate, a first terminal, and a second terminal;
an eighth transistor including a gate configured to receive a second writing signal, a first terminal connected to a second data line, and a second terminal connected to the first terminal of the seventh transistor;
a ninth transistor including a gate configured to receive the first emission signal, a first terminal connected to a line associated with transferring a power supply voltage, and a second terminal connected to the first terminal of the seventh transistor;
a tenth transistor including a gate configured to receive a fourth writing signal, a first terminal connected to the second terminal of the seventh transistor, and a second terminal connected to the gate of the seventh transistor;
a second capacitor including a first electrode connected to the line associated with transferring the power supply voltage and a second electrode connected to the gate of the seventh transistor;
an eleventh transistor including a gate configured to receive the first emission signal, a first terminal connected to the second terminal of the seventh transistor, and a second terminal connected to the anode of the light emitting element; and
a twelfth transistor including a gate configured to receive a second emission signal, a first terminal connected to the second terminal of the first transistor, and a second terminal connected to the gate of the seventh transistor”, as claimed.
Conclusion
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/DAVID TUNG/Primary Examiner, Art Unit 2622
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