DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Coursey (United States Patent Application Publication No. US 2003/0215998 A1, hereinafter “Coursey”) in view of Govindarajan (United States Patent Application Publication No. US 2006/0151822 A1, hereinafter “Govindarajan”).
In reference to claim 1, Coursey discloses a similar device. Fig. 9-28 of Coursey disclose a semiconductor device which comprises a gate structure (20, 22, 24) disposed on a substrate (12). A plurality of insulating spacers (26) is disposed on the substrate (12) and located at opposite sides of the gate structure (20, 22, 24). A plurality of first pads (28) is disposed on the plurality of insulating spacers (26). An insulating layer (116, 118) overlies the plurality of insulating spacers (26) and the gate structure (20, 22, 24). A portion of the insulating layer (116, 118) overlying the gate structure (20, 22, 24) has a recess. A capacitor dielectric layer (222) is disposed in the recess wherein a bottommost surface of the capacitor dielectric layer (222) is lower than a topmost surface of the first pads (28). Coursey does not disclose that the capacitor dielectric layer (222) is made from a high dielectric constant dielectric material. However Govindarajan discloses that the use of high dielectric constant dielectric material as a capacitor dielectric material leads to a capacitor with a high capacitance (p. 3, paragraph 35) which is desirable in the art (p. 1, paragraphs 5-6). In view of Govindarajan, it would therefore be obvious to implement a high dielectric constant dielectric material for the capacitor dielectric layer (222) in the Coursey device.
Allowable Subject Matter
Claims 9-20 are allowed.
Claims 2-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: in the examiner’s opinion, it would not be obvious to implement a semiconductor device with a substrate having first and second regions such that there is gate structure disposed in the first region having a plurality of insulating spacers on opposite sides of the gate structure in combination with the specific first pads, pad spacers, and first spacer structure described by the applicant in claim 9. In the examiner’s opinion, it would also not be obvious to implement a semiconductor device with a gate structure disposed on a substrate having a plurality of insulating spacers on opposite sides of it with a plurality of first pads on the insulating spacers such that there is an insulating layer over the plurality of insulating spacers and the gate structure with a portion of the insulating layer overlying the gate structure having a recess with a high dielectric constant dielectric layer disposed in it with a bottommost surface of the high dielectric constant dielectric layer being lower than a topmost surface of the first pads in combination with the specific pad spacers, first spacer structure, relative heights of the first pad and high dielectric constant dielectric layer, and second pads described by the applicant in claims 2 and 6-8.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN QUINTO whose telephone number is (571)272-1920. The examiner can normally be reached Monday-Friday, 9-5:30.
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/KEVIN QUINTO/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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