DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 02/10/2026 have been fully considered but they are not persuasive.
First, Applicant argues that Hadrick does not disclose generating an alert signal based on pulses or time intervals of a CRC signal. The rejection does not rely on Hadrick alone for these features. As explained in the Office Action, Hadrick teaches a memory device configured to detect CRC errors during data transmission and to generate an alert signal when a CRC error is detected (Hadrick, e.g., col. 3–4). The rejection relies on Luo for the well-known technique of representing events using pulse signals and determining system conditions based on time intervals between adjacent pulses.
Second, Applicant contends that Luo teaches away from CRC because it states that CRC checks are not required in its communication frame. This argument is not persuasive. Luo’s statement merely indicates that CRC is not required for the particular communication protocol described in Luo. This does not constitute a teaching away from the general use of pulse timing analysis, which is the feature relied upon in the rejection. The rejection relies on Luo only for monitoring time intervals between pulses and generating signals based on those intervals, not for CRC detection itself.
Third, Applicant argues that Luo uses pulse intervals to encode data rather than generate alert signals. However, the specific purpose for which a known technique is used does not limit its applicability. Luo clearly teaches that system states or information can be determined based on the interval between adjacent pulses, which would have suggested to one of ordinary skill in the art the use of pulse interval comparison to detect abnormal conditions or error events in other systems, including CRC error signaling in memory devices such as Hadrick.
Fourth, Applicant argues that Luo does not generate two pulses corresponding to two adjacent pulses in the CRC signal. However, Luo teaches detecting relationships between adjacent pulses and generating corresponding signals based on those relationships. Adapting such pulse-interval detection to CRC error pulses in Hadrick would have been a predictable design choice for identifying closely spaced error events and generating a corresponding alert.
Finally, Applicant’s argument regarding the technical problem is not persuasive. The rejection is based on whether the claimed features would have been obvious to a person of ordinary skill in the art, not whether the references address the identical problem described in the specification. It is well established that references may be combined where they teach analogous techniques applicable to similar signal-processing problems, as is the case here.
Accordingly, the combination of Hadrick and Luo continues to teach or suggest the limitations of claim 1. The arguments presented for dependent claims 19 and 20 are also not persuasive because pulse characteristics such as pulse width and timing relationships are well-known design parameters in pulse-based signaling systems and would have been obvious design choices.
Therefore, the rejection of claims 1–20 under 35 U.S.C. §103 is maintained. Applicant is invited to amend the claims to further distinguish over the applied prior art.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hadrick (US 10,388,362 B1) and further in view of Luo (CN 101639819 A).
Claim 1: Hadrick teaches a memory device, comprising: a cyclic redundancy check (CRC) circuit, configured to indicate whether a CRC error has been detected from data transmission between a host device and the memory device (e.g. Hadrick teaches:
a memory device with a command interface and I/O interface for data transmission between a host and the memory device (e.g. Fig. 1, col. 4, lines 4-16);
An ALERT signal that is transmitted from the memory device when a CRC error is detected, (e.g. col. 5, lines 40-45); and
Control logic (e.g., command decoder, bank control circuitry, Fig. 1) that generates timing and control signals, including strobe signals with pulses (Fig. 4, col. 7, lines 3-42).
Not explicitly taught by Hadrick is a CRC circuit that generates a CRC signal with N pulses corresponding to N CRC errors and an alert signal generation module, configured to generate an alert signal when a time interval between any two adjacent pulses in the CRC signal is less than or equal to a first preset time interval, the alert signal having two pulses corresponding to the two adjacent pulses in the CRC signal.
However, Luo provides the missing teachings regarding interval-based error detection and signaling. For instance, Luo teaches a communication system that detects errors by monitoring time intervals between pulses (Claim 1, 3). Luo further teaches declaring an "error" state is declared when the pulse interval is less than 0.875T (a preset time interval) (Claim 3), and generating signals (including error states) based on these interval measurements (Claim 4). Luo additionally teaches that its system is self-synchronizing using pulse edges, making each pulse a synchronization event (Claim 2).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Hadrick's memory device with Luo's interval-based error detection to provide more granular error reporting.
As per claim 13, the claimed features are rejected similarly to claim 1 above.
Claim 2: Hadrick and Luo teach the memory device according to claim 1, wherein the alert signal generation module comprises a first delay unit, a second delay unit, and an alert signal generation unit (e.g. Hadrick teaches a column logic (154) with a chain of delay blocks (202A, 202B, 204) for generating timed control signals, Fig. 6, col. 8, lines 27-44).
Not explicitly taught by Hadrick and Luo is that the first delay unit being configured to perform a delay operation on the CRC signal, and generate a first delayed signal; the second delay unit being configured to perform a delay operation on the first delayed signal, and generate a second delayed signal and a third delayed signal, the third delayed signal being delayed by a second preset time interval relative to the second delayed signal; and the alert signal generation unit being configured to generate the alert signal based on the first delayed signal, the second delayed signal, and the third delayed signal, the alert signal comprising at least one pulse with a width of the second preset time interval. However, Luo’s system inherently requires measuring time intervals, which it performs using delay elements and associated generation units (e.g., timers or processing circuits). A POSITA would have recognized that Hadrick’s delay chain operates as a flexible timing circuit capable of producing controlled temporal measurements. Accordingly, to incorporate Luo’s interval-checking functionality into Hadrick, it would have been an obvious and predictable design choice, to a POSITA before the effective filing date of the claimed invention, to adapt Hadrick’s existing delay chain to compare a measured interval against a predetermined threshold and to assert an alert when the interval falls below that threshold. Such a modification would merely apply a known timing-based error-detection technique to an existing timing circuit and would yield a predictable result.
As per claim 14, the claimed features are rejected similarly to claim 2 above.
Claim 3: Hadrick and Luo teach the memory device according to claim 2, but fail to teach that the second delay unit is a shift register, a length value of the shift register is M, and M is an integer greater than or equal to (T+1). However, Hadrick describes delay elements within the column logic chain (e.g. col. 8, lines 28-29). In other words, Hadrick's delay chains (Fig. 6) could be implemented with shift registers. And a shift register is a well-known and conventional digital circuit element used for creating precise delays. Faced with the need to build a delay unit from Hadrick, a POSITA, before the effective filing date of the claimed invention, would have been motivated to select a shift register, which is a standard technical mean to achieve the required delay.
Claim 4: Hadrick and Luo teach the memory device according to claim 3, but fail to teach that the shift register comprises: M-stage flip-flops, clock terminals of M flip-flops constituting the M-stage flip-flops receiving a same clock signal, an output port Q of each current-stage flip-flop in the M-stage flip-flops being connected to an input port D of a next-stage flip-flop, an input port D of a first-stage flip-flop receiving the first delayed signal, an output port Q of the first-stage flip-flop being connected to a first input terminal of the alert signal generation unit, and outputting the second delayed signal delayed by one clock cycle to the alert signal generation unit; and an output port Q of an Mth-stage flip-flop being connected to a second input terminal of the alert signal generation unit, and outputting the third delayed signal delayed by M clock cycles to the alert signal generation unit. However, Hadrick describes delay elements within the column logic chain (e.g. col. 8, lines 28-29). In other words, Hadrick's delay chains (Fig. 6) could be implemented with shift registers. And a shift register is a well-known and conventional digital circuit element used for creating precise delays. Faced with the need to build a delay unit from Hadrick, a POSITA, before the effective filing date of the claimed invention, would have been motivated to select a shift register, which is a standard technical mean to achieve the required delay. The specific implementation details (M-stages, clock connections) are routine design choices within the ordinary skill of a digital circuit designer.
Claim 5: Hadrick and Luo teach the memory device according to claim 4, but fail to teach that the CRC signal serves as a reset signal for the M flip-flops of the shift register. However, Hadrick teaches that the strobe signal (153) drives the delay chain (e.g. col. 8, lines 28-29). And in digital logic design, using a significant event signal (like an error pulse) to reset or synchronize a timing circuit is a standard practice to ensure accurate measurement. Therefore, a POSITA, before the effective filing date of the claimed invention, seeking to measure intervals between CRC errors would have been motivated to use the CRC pulses themselves to reset the timing circuit (shift register). This ensures each measurement starts fresh, a predictable application of a known technique to a new but analogous signal.
Claim 6: Hadrick and Luo teach the memory device according to claim 5, but fail to teach that the alert signal generation unit comprises a latch unit and a logical operation unit, the latch unit being configured to receive the second delayed signal and the third delayed signal, and output a pre-alert signal; and the logical operation unit being configured to receive the pre-alert signal and the first delayed signal, and output the alert signal. However, Hadrick teaches, in col. 8, lines 64-67 and col. 9, lines 24-27), that the delay chain outputs are gated with enable signals using logic elements (226, 248, 250). And an SR latch is a fundamental memory element for storing a state, and NAND gates and inverters are basic building blocks of digital systems. Therefore, a POSITA, before the effective filing date of the claimed invention, would have been motivated to combine these common logic components to create a circuit that latches an alert condition. This is a predictable use of these elements according to their established functions in digital design to achieve the desired control logic, with any specific arrangement being a matter of routine optimization.
Claim 7: Hadrick and Luo teach the memory device according to claim 6, but fail to teach that the latch unit comprises an SR latch, and a set port of the SR latch serves as the first input terminal of the alert signal generation unit, and is connected to the output port Q of the first-stage flip-flop; and a reset port of the SR latch serves as the second input terminal of the alert signal generation unit, and is connected to the output port Q of the Mth-stage flip-flop, and an output terminal of the SR latch is connected to an input terminal of the logical operation unit. However, Hadrick teaches, in col. 8, lines 64-67 and col. 9, lines 24-27), that the delay chain outputs are gated with enable signals using logic elements (226, 248, 250). And an SR latch is a fundamental memory element for storing a state, and NAND gates and inverters are basic building blocks of digital systems. Therefore, a POSITA, before the effective filing date of the claimed invention, would have been motivated to combine these common logic components to create a circuit that latches an alert condition. This is a predictable use of these elements according to their established functions in digital design to achieve the desired control logic, with any specific arrangement being a matter of routine optimization.
Claim 8: Hadrick and Luo teach the memory device according to claim 7, but fail to teach that the logical operation unit comprises an inverter and a logic NAND gate, and an input terminal of the inverter is connected to an output port of the first delay unit, and is configured to receive the first delayed signal; and output terminals of the SR latch and the inverter are connected to an input terminal of the logic NAND gate, and the logic NAND gate receives the pre-alert signal and the first delayed signal subjected to a logical NOT operation, and outputs the alert signal. However, Hadrick teaches, in col. 8, lines 64-67 and col. 9, lines 24-27), that the delay chain outputs are gated with enable signals using logic elements (226, 248, 250). And an SR latch is a fundamental memory element for storing a state, and NAND gates and inverters are basic building blocks of digital systems. Therefore, a POSITA, before the effective filing date of the claimed invention, would have been motivated to combine these common logic components to create a circuit that latches an alert condition. This is a predictable use of these elements according to their established functions in digital design to achieve the desired control logic, with any specific arrangement being a matter of routine optimization.
Claim 9: Hadrick and Luo teach the memory device according to claim 2, wherein the second delayed signal is delayed by at least one clock cycle relative to the first delayed signal (e.g. Hadrick’s Fig. 6: the delay chain produces signals that are sequentially delayed.
As per claim 15, the claimed features are rejected similarly to claim 9 above.
Claim 10: Hadrick and Luo teach the memory device according to claim 9, but fail to teach that the first preset time interval is T clock cycles, and T is an integer greater than or equal to 1 and less than or equal to 12. However, Hadrick teaches, in col. 3, lines 52-59, memory devices operating with precise clock cycles and timing intervals and Luo explicitly teaches using specific time intervals measured in units of T for error detection (Claim 3: "data '0'=T", "error"<0.875T"), Therefore, a POSITA, before the effective filing date of the claimed invention, seeking to implement Luo's interval-based error detection in Hadrick's memory device would have been motivated to quantify the "first preset time interval" in clock cycles, as clock cycles are the fundamental timing unit in digital memory systems. The specific range of 1-12 clock cycles represents a reasonable design choice for detecting rapid error bursts without being overly sensitive to single errors. This is a predictable optimization within the ordinary skill of memory system designers.
As per claim 16, the claimed features are rejected similarly to claim 10 above.
Claim 11: Hadrick and Luo teach the memory device according to claim 10, but fail to teach that a length of the second preset time interval is greater than or equal to T clock cycles. However, Hadrick's delay chain (Fig. 6) inherently creates multiple delayed signals with specific timing relationships and the timing relationships between different delayed signals are carefully controlled to ensure proper operation. Furthermore, Luo's system uses multiple timing thresholds (0.875T, 1.125T, 1.5T) that maintain specific relationships to the base unit T (see page 2, paragraph 3). Besides, in digital circuit design, maintaining consistent timing relationships between different signals is a fundamental design principle. Therefore, a POSITA, before the effective filing date of the claimed invention, implementing the interval monitoring circuit would have recognized that the second preset time interval (which defines the alert pulse width) should be coordinated with the first preset time interval (which defines the error detection threshold).Thus, setting the second interval to be ≥ T clock cycles ensures the alert pulse has sufficient duration to be reliably detected, representing a predictable design choice for signal integrity.
As per claim 17, the claimed features are rejected similarly to claim 11 above.
Claim 12: Hadrick and Luo teach the memory device according to claim 11, but fail to teach that a sum of a delay applied by the first delay unit to the CRC signal and one clock cycle is less than 13 ns. However, Hadrick operates in high-speed memory environments with nanosecond-scale timing constraints (e.g. DDR5 SDRAM devices operating at GHz frequencies- col. 3, lines 39-51). And Luo teaches setting specific timing constraints to meet system requirements is routine engineering practice. Thus, the value of 13 ns represents a conventional timing budget for error reporting in high-speed memory systems. Therefore, a POSITA, before the effective filing date of the claimed invention, designing for high-speed memory applications would have been motivated to constrain the total delay path to ensure timely error reporting.The specific limit of less than 13 ns represents a predictable design constraint based on typical memory clock frequencies and system response requirements. This is a routine optimization in memory interface design.
Claim 18: Hadrick and Luo teach the control method according to claim 15, but fail to teach that the third delayed signal is delayed by M clock cycles relative to the first delayed signal, and M is an integer greater than or equal to (T+1). However, Hadrick teaches delay chains with multiple delay elements that create precisely timed signals (Fig. 6); the column logic (154) includes multiple delay blocks (202A, 202B, 204) that generate signals with specific timing relationships. Thus, Hadrick's system inherently creates signals delayed by multiple clock cycles relative to input signals. Furthermore, Luo explicitly teaches using shift registers with specific length relationships to timing parameters (Claim 3: "the length value of the shift register is M, and M is an integer greater than or equal to (T+1)"). The relationship M is an integer greater than or equal to (T+1) represents a conventional design constraint to ensure proper timing margins in digital circuits and using integer clock cycle delays and establishing mathematical relationships between timing parameters is routine engineering practice. Therefore, a POSITA, before the effective filing date of the claimed invention, implementing the interval monitoring method of Luo in Hadrick's memory device would have been motivated to use clock-cycle-based delays (as taught by Hadrick's timing circuits) and to establish the specific mathematical relationship M ≥ (T+1) (as explicitly taught by Luo for proper circuit operation) in order to ensure the third delayed signal has sufficient delay relative to the detection threshold T, which is a routine design consideration for proper circuit operation.
Claim 19: Hadrick and Luo teach the memory device of claim 1, but fail to teach that a pulse width of a first one of the two pulses of the alert signal is less than or equal to a pulse width of a second one of the two pulses of the alert signal. However, pulse width selection is a well-known design parameter in pulse-based signaling systems. Therefore, a POSITA would have found it obvious to adjust pulse widths (e.g., increasing width for later pulses) to improve signal detection, timing margin, or reliability, particularly when signaling closely spaced error events.
Thus, the claimed width relationship represents an obvious design choice involving routine optimization of pulse characteristics.
Claim 20: Hadrick and Luo teach the memory device of claim 1, but fail to teach that when a time interval between only two adjacent pulses in the CRC signal is less than or equal to the first preset time interval, a pulse width of a first one of the two pulses of the alert signal is less than a pulse width of a second one of the two pulses of the alert signal. However, once the system uses pulse-based signaling determined by timing relationships between adjacent pulses (Luo) and CRC error signaling (Hadrick), modifying the relative pulse widths of alert pulses is a predictable variation and routine design choice to improve signal distinguishability or encode additional information about the detected event. And such a modification would have been within the general knowledge of an artisan in the art.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 3/25/2026
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