DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7,11,13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nagata et al., (Nagata) US 2017/0062574 in view of Laforet et al., (Laforet) US 2017/0110573.
Regarding claim 1, Nagata discloses and shows in FIG. 1-11, a semiconductor device, comprising: a semiconductor layer (1)[0039]; a gate trench (13)[0044] formed in the semiconductor layer (1) and; a field plate trench (14)[0045] formed in the semiconductor layer (1), the field plate trench (14) being surrounded by the gate trench (13)(part could be duplicated, see case law below) in plan view and being separated from the gate trench (13); an insulation layer (40)[0062] formed on the semiconductor layer; a gate electrode (21)[0062] arranged in the gate trench (13), the gate electrode (21) including an upper surface covered by the insulation layer (40) and a bottom surface opposite to the upper surface; a first field plate electrode (22)[0072] arranged in the gate trench (13) below the bottom surface of the gate electrode (21); a second field plate electrode (32)[0058] arranged in the field plate trench (14), the second field plate electrode (32) including an upper surface covered by the insulation layer; and a source electrode (4)[0064] formed on the insulation layer, wherein the first field plate electrode (22) and the second field plate electrode (32) are electrically connected to the source electrode (4).
Nagata differs from the claimed invention because he does not explicitly disclose a device having a gate trench arranged in a mesh pattern in plan view.
Laforet discloses [0079], a device having a gate trench (150a) arranged in a mesh pattern in plan view.
Laforet is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Nagata. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Laforet in the device of Nagata because it will improve the switching characteristics of semiconductor devices [0002].
As for the multiple field plates, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to have multiple field plates, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. 2144.04
Regarding claim 2, Nagata in view of Laforet discloses a semiconductor device further comprising: a first contact plug (45)[0064] configured to couple the second field plate electrode (32)[0058] to the source electrode (4), wherein the first contact plug (45) extends through the insulation layer (40) between the upper surface of the second field plate electrode (32) and the source electrode (4).
Regarding claim 3, Nagata in view of Laforet discloses a semiconductor device wherein the first contact plug (45) overlaps the field plate trench (14) in plan view.
Regarding claim 4, Nagata in view of Laforet discloses a semiconductor device wherein the field plate trench (14) is cross-shaped in plan view.
Regarding claim 5, Nagata in view of Laforet discloses a semiconductor device wherein the field plate trench (14) is rectangular in plan view (see also Laforet).
Regarding claim 6, Nagata in view of Laforet discloses a semiconductor device wherein the field plate trench (14) includes a first trench extending in a first direction in plan view, and a second trench (14 other) and a third trench that are separated from the first trench and extend in a second direction that is orthogonal to the first direction in plan view, the first trench extending between the second trench and the third trench in plan view (see also trenches in FIG. 8).
Laforet is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Nagata. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Laforet in the device of Nagata because it will improve the switching characteristics of semiconductor devices [0002].
Regarding claim 7, Nagata in view of Laforet discloses a semiconductor device wherein the semiconductor layer includes a drift region (18)[0046] of a second conductivity type (n-), a body region (16)[0046] of a first conductivity type formed on the drift region (18), and a source region (15)[0046] of the second conductivity type formed on the body region, and the gate trench (13) and the field plate trench (14) extend through the source region (15) and the body region to the drift region (18).
Regarding claim 11, Nagata in view of Laforet discloses a semiconductor device wherein the second field plate electrode (32) includes a bottom surface opposite to the upper surface, and the semiconductor device further comprises a third field plate (33)[0058] electrode arranged below the bottom surface of the second field plate electrode (32) in the field plate trench.
Regarding claim 13, Nagata in view of Laforet discloses a semiconductor device wherein the semiconductor layer includes mesh cells [0079] surrounded by the gate trench, and the mesh cells are each rectangular in plan view [0079, 0110].
Regarding claim 14, Nagata in view of Laforet discloses a semiconductor device wherein the semiconductor layer includes mesh cells surrounded by the gate trench [0079, 0110], and the mesh cells are each square in plan view [0079, 0110].
Regarding claim 15, Nagata in view of Laforet discloses a semiconductor device wherein the field plate trench is one of multiple field plate trenches respectively arranged in the mesh cells [0110,0142].
Allowable Subject Matter
Claims 8-10, 12 are objected to as being dependent upon a rejected base claim 1, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARC-ANTHONY ARMAND whose telephone number is (571)272-5178. The examiner can normally be reached 8am-5pm.
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MARC - ANTHONY ARMAND
Primary Examiner
Art Unit 2813
/MARC-ANTHONY ARMAND/Primary Examiner, Art Unit 2813
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