DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the vertical channel layer" in line 8. There is insufficient antecedent basis for this limitation in the claim.
It appears that “the vertical channel layer” intends to refer to “a channel layer” of line 5. Interpretations will be based on this assumption.
Claim 15 recites the limitation "the liner layer" in line 1. There is insufficient antecedent basis for this limitation in the claim.
It appears that “the liner layer” intends to refer to “a liner layer” of claim 17, line 2.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 9, 12, and 16-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (U.S. Publication No. 2019/0326315 A1; hereinafter Lee)
With respect to claim 1, Lee discloses a semiconductor device, comprising: an alternating stack [ST] that is disposed over a lower structure [10] and includes gate electrodes [EGE,CGE,SGE] and dielectric layers [12] which are staked alternately; a memory stack structure that includes a channel layer [VS] extending to penetrate through the alternating stack (See ¶[0068]), and a memory layer [DSP] surrounding the channel layer; a source layer [SCP1] in contact with an outer wall of the vertical channel layer and disposed over the alternating stack; a trench [112] spaced apart from the memory stack structure and extending to penetrate through the alternating stack (See Figure 7H); and a sealing spacer [SS] suitable for sealing the gate electrodes and disposed between the trench and the gate electrodes (see Figure 7J), the sealing spacer having a thickness in a horizontal direction smaller than a thickness of each of the dielectric layers and the gate electrodes in a vertical direction (See Figure 7J).
With respect to claim 9, Lee discloses wherein an outer wall of the trench is surrounded by the sealing spacer, and wherein the sealing spacer extends in a specific direction to cover the gate electrodes, the dielectric layers, and the source layer, the gate electrodes and the dielectric layers being stacked in the specific direction (See Figure 4).
With respect to claim 12, Lee discloses an upper source layer [SCP2] between the alternating stack and the source layer; and a lower source layer [341] between the source layer and the lower structure, wherein each of the upper source layer and the lower source layer includes a semiconductor material (See ¶[0054] and ¶[0056]).
With respect to claim 16, Lee discloses wherein the dielectric layers [12] of the alternating stack include a bottom dielectric layer, the remaining dielectric layers of the alternating stack disposed over the bottom dielectric layer, the bottom dielectric layer having a thickness thinner than that of each of the remaining dielectric layers (see Figure 4)
With respect to claim 17, Lee discloses a liner layer [30C] between the alternating stack and the source layer (See Figure 9).
With respect to claim 18, Lee discloses wherein the liner layer and the sealing spacer include the same material (See ¶[0092]).
With respect to claim 19, Lee discloses wherein a top dielectric layer [12] among the dielectric layers is thicker than the dielectric layers at lower levels than the top dielectric layer (See Figure 4).
With respect to claim 20, Lee discloses wherein the dielectric layers include SiO2 (See ¶[0049])
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 10, and 21-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Huo et al. (U.S. Publication No. 2020/0395373 A1; hereinafter Huo).
With respect to claim 2, Lee fails to disclose wherein the thickness of a protrusion of the sealing spacer in the horizontal direction is smaller than the thickness of each of the dielectric layers and the gate electrodes in the vertical direction as Lee does not contain protrusions. In the same field of endeavor, Huo teaches the thickness of a protrusion of the sealing spacer [142] in the horizontal direction is smaller than the thickness of each of the dielectric layers and the gate electrodes in the vertical direction (See Figure 8C). Implementation of protrusions in the sealing spacer increase the overall support of the 3D memory device, increasing the structural stability (See Huo ¶[0070]) and increased isolation to minimize fluctuations (See Huo ¶[0044]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention. With respect to claim 10, Lee fails to disclose wherein the sealing spacer includes one or more protrusions extending in a specific direction to seal one or more ends of the gate electrodes, respectively, the specific direction being perpendicular to a direction in which the gate electrodes and the dielectric layers are stacked. In the same field of endeavor, Huo teaches wherein the sealing spacer includes one or more protrusions extending in a specific direction to seal one or more ends of the gate electrodes, respectively, the specific direction being perpendicular to a direction in which the gate electrodes and the dielectric layers are stacked (See Figure 8C). Implementation of protrusions in the sealing spacer increase the overall support of the 3D memory device, increasing the structural stability (See Huo ¶[0070]) and increased isolation to minimize fluctuations (See Huo ¶[0044]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 21, Lee fails to disclose wherein ends of the dielectric layers have a shape that is horizontally recessed from the ends of the dielectric layers.
In the same field of endeavor, Huo teaches wherein ends of the dielectric layers have a shape that is horizontally recessed from the ends of the dielectric layers (See Figure 8C). Implementation of recesses allow for better integration with the sealing spacer thereby increase the overall support of the 3D memory device, increasing the structural stability (See Huo ¶[0070]) and increased isolation to minimize fluctuations (See Huo ¶[0044]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 22, Lee fails to disclose wherein the sealing spacer includes one or more protrusion that is coupled to the ends of the gate electrodes, respectively.
In the same field of endeavor, Huo teaches wherein the sealing spacer includes one or more protrusion that is coupled to the ends of the gate electrodes, respectively (See Figure 8C). Implementation of protrusions in the sealing spacer increase the overall support of the 3D memory device, increasing the structural stability (See Huo ¶[0070]) and increased isolation to minimize fluctuations (See Huo ¶[0044]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 23, Lee fails to disclose wherein a thickness of a protrusion of the sealing spacer in the horizontal direction is smaller than a thickness of each of dielectric layers and the gate electrodes in the vertical direction.
In the same field of endeavor, Huo teaches wherein a thickness of a protrusion of the sealing spacer in the horizontal direction is smaller than a thickness of each of dielectric layers and the gate electrodes in the vertical direction (See Figure 8C). Implementation of protrusions in the sealing spacer increases the overall support of the 3D memory device, increasing the structural stability (See Huo ¶[0070]) and increased isolation to minimize fluctuations (See Huo ¶[0044]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 24, Lee fails to disclose wherein a protrusion of the sealing spacer has a thickness in range from 50 Å to 100 Å in the horizontal direction.
In the same field of endeavor, Huo teaches wherein a protrusion of the sealing spacer (See Figure 8C). Implementation of protrusions in the sealing spacer increases the overall support of the 3D memory device, increasing the structural stability (See Huo ¶[0070]) and increased isolation to minimize fluctuations (See Huo ¶[0044]). Huo is silent as to the specific thicknesses of the protrusions, however it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention to implement a proper thickness of the protrusions to eliminate any short circuiting between the source contact plug and gate structures. Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 3-4, 6-8 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Lilak et al. (U.S. Publication No. 2020/0403033 A1; hereinafter Lilak)
With respect to claim 3, Lee fails to disclose wherein the sealing spacer includes a carbon-containing material.
In the same field of endeavor, Lilak teaches the sealing spacer includes a carbon-containing material (See ¶[0032]). Implementation of a carbon-containing material in the low-k dielectric of Lee, as taught by Lilak, reduces parasitic capacitance (see Lilak ¶[0027]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 4, Lee fails to disclose wherein the sealing spacer includes a carbon-containing silicon oxide.
In the same field of endeavor, Lilak teaches wherein the sealing spacer includes a carbon-containing silicon oxide (See ¶[0032]). Implementation of a carbon-containing material in the low-k dielectric of Lee, as taught by Lilak, reduces parasitic capacitance (see Lilak ¶[0027]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 6, Lee fails to disclose wherein the sealing spacer includes SiCO (See ¶[0032]). Implementation of a carbon-containing material in the low-k dielectric of Lee, as taught by Lilak, reduces parasitic capacitance (see Lilak ¶[0027]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 8, Lee fails to disclose wherein the sealing spacer includes SiCO, and a carbon content of SiCO is less than a silicon content and an oxygen content.
In the same field of endeavor, Lilak teaches wherein the sealing spacer includes SiCO, and a carbon content of SiCO is less than a silicon content and an oxygen content (See ¶[0032]).
Implementation of a carbon-containing material in the low-k dielectric of Lee, as taught by Lilak, reduces parasitic capacitance (see Lilak ¶[0027]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 15, Lee fails to disclose wherein the liner layer and the sealing spacer include a carbon-containing silicon oxide, but does disclose wherein the liner layer and the sealing spacer are the same material (See ¶[0092]).
In the same field of endeavor, Lilak teaches wherein the liner layer and the sealing spacer include a carbon-containing silicon oxide (See ¶[0032]).
Implementation of a carbon-containing material in the low-k dielectric of Lee, as taught by Lilak, reduces parasitic capacitance (see Lilak ¶[0027]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Yon et al. (U.S. Publication No. 2015/0372005 A1; hereinafter Yon).
With respect to claim 5, Lee fails to disclose wherein the sealing spacer includes a material that has a wet-etch resistance greater than that of SiO2 and a dielectric constant lower than that of silicon nitride, however does disclose the utilization of a low-k material within other regions of the device (See ¶[0049]; low-k dielectric layer).
In the same field of endeavor, Yon teaches the sealing spacer includes a material that has a wet-etch resistance greater than that of SiO2 and a dielectric constant lower than that of silicon nitride (see ¶[0073]). Implementation of low-k materials for the sealing spacer allows for higher control during processing of the device and formation of the source plug regions. Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee.
With respect to claim 11, Lee fails to explicitly disclose wherein the sealing spacer has a thickness in a range from 50 Å to 100 Å, however it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention to implement a proper thickness of the sealing spacer to eliminate any short circuiting between the source contact plug and gate structures.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Jung et al. (U.S. Publication No. 2019/0027434 A1; hereinafter Jung).
With respect to claim 14, Lee fails to disclose wherein the sealing spacer includes SiCN, SiBCN, or SiBN.
In the same field of endeavor, Jung teaches the sealing spacer [192] includes SiCN, SiBCN, or SiBN (See ¶[0108]). The implementation of a functionally equivalent dielectric material as taught by Jung would allow for proper electrical isolation of the gate from the source contact plug. Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention.
Allowable Subject Matter
Claims 7-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 7, none of the prior art teaches or suggests, alone or in combination, wherein the sealing spacer includes a stack of a layer of SiO2 and a layer of SiCO, and the SiCO layer is in direct contact with the trench.
With respect to claim 13, none of the prior art teaches or suggests, alone or in combination, trench includes: a silicon-containing material pattern; a metal-containing material pattern disposed over the silicon-containing material pattern; and a barrier material layer disposed between the silicon-containing material pattern and the metal-containing material pattern.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gunji-Yoneoka et al. (U.S. Patent No. 10,121,794 B2) discloses a three
dimensional memory device.
Lee et al. (U.S. Publication No. 20160190155 A1) discloses a three
dimensional memory
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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