Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “approximately 1/3 to approximately 1/2 times a diameter” in claim11 is a relative term which renders the claim indefinite. The term “approximately” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
In order to expedite prosecution, the term “approximately 1/3 to approximately 1/2 times a diameter” in claim 11 is construed as how it might be interpreted by a person having ordinary skill in the art.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6 and 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over “Ishihara” (2017/0215282) in view of “Kita” (US 2019/0371717).
Regarding claim 1, Ishihara discloses 1. A wiring board comprising: a first insulating layer (Figs. 2C, 3D-4C, [0023], [0031], [0035], [0039], [0046]; the insulating layer 50A is a first insulating layer);
a first interconnect layer formed on the first insulating layer (Figs. 2C, 3D-4C, [0023], [0031], [0035], [0039], [0046]; the conductor layer 34, Fig. 2C is a first conductor layer formed on the insulating layer 50A);
a second insulating layer formed on the first interconnect layer (Figs. 2C, 3D-4C, [0023], [0031], [0035], [0039], [0046]; the insulating layer 50C is a second insulating layer formed on the conductor layer 34);
an opening penetrating the second insulating layer and exposing an upper surface of the first interconnect layer (Figs. 2C, 3D-4C, [0023], [0031], [0035], [0039], [0046]; the via 36C is an opening penetrating the insulating layer 50C and exposing an upper surface of the conductor layer 34);
and a second interconnect layer that is an outermost interconnect layer disposed inside the opening and electrically connected to the first interconnect layer (Figs. 2C, 3D-4C, [0023], [0031], [0035], [0039], [0046]; the conductor layer 58B1 is a second interconnect layer that is an outermost interconnect layer disposed inside the opening and electrically connected to the conductor layer 34).
Ishihara does not disclose the opening includes an inner surface formed by a surface of the second insulating layer defining the opening, and a bottom surface formed by the upper surface of the first interconnect layer, the second interconnect layer includes a seed layer continuously covering the inner surface and the bottom surface of the opening, and an end surface of the seed layer, oriented upward toward an upper surface of the second insulating layer, is located below the upper surface of the second insulating layer.
Kita discloses the opening includes an inner surface formed by a surface of the second insulating layer defining the opening (Fig. 1, 5A-C, [0029]-[0033], [0039], [0041], [0051]; the via hole 10x is an opening formed by a surface of the solder resist layer 50 which is the second insulating layer, defining the opening),
and a bottom surface formed by the upper surface of the first interconnect layer, the second interconnect layer includes a seed layer continuously covering the inner surface and the bottom surface of the opening (Fig. 1, 5A-C, [0029]-[0033], [0039], [0041], [0051]; a bottom surface formed by the upper surface of the conductive layer 22 which is the first interconnect layer, the interconnect layer 42 is the second interconnect layer which includes the adhesion layer 41 which is a seed layer, continuously covering the inner surface and the bottom surface of the via hole 10x),
and an end surface of the seed layer, oriented upward toward an upper surface of the second insulating layer, is located below the upper surface of the second insulating layer (Fig. 1, 5A-C, [0029]-[0033], [0039], [0041], [0051]; an end surface of the adhesion layer 41, oriented upward toward an upper surface of the solder resist layer 50, is located below the upper surface of the solder resist layer 50).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Ishihara’s wiring board with Kita’s via holes in order to provide an interconnect substrate for which haloing is less likely to occur to reduce the incidence of fracturing and delamination resulting from mechanical causes, as suggested by Kita at [0005].
Regarding claim 2, Ishihara in view of Kita discloses the claimed invention as applied to claim 1, above.
Ishihara discloses 2. The wiring board as claimed in claim 1, wherein the seed layer serves as an adhesion layer (Figs. 2C, 3D-4C, [0023], [0031], [0035], [0039], [0046]; the seed layer 52C serves as an adhesion layer).
Regarding claim 3, Ishihara in view of Kita discloses the claimed invention as applied to claim 1, above.
Ishihara discloses 3. The wiring board as claimed in claim 1, wherein the second insulating layer covers the first interconnect layer (Figs. 2C, 3D-4C, [0023], [0031], [0035], [0039], [0046]; the insulating layer 50C covers the insulating layer 50A).
Regarding claim 4, Ishihara in view of Kita discloses the claimed invention as applied to claim 1, above.
Ishihara discloses 4. The wiring board as claimed in claim 1, further comprising: a third insulating layer covering the first interconnect layer and disposed between the first insulating layer and the second insulating layer (Figs. 2C, 3D-4C, [0023], [0031], [0035], [0039], [0046]; the insulating layer 50B is a third insulating layer covering the conductor layer 34 and disposed between the insulating layer 50A and the insulating layer 50C),
wherein the opening penetrates the second insulating layer and the third insulating layer and exposes the upper surface of the first interconnect layer (Figs. 2C, 3D-4C, [0023], [0031], [0035], [0039], [0046]; the opening penetrates the insulating layer 50C and the insulating layer 50B and exposes the upper surface of the conductor layer 34).
Regarding claim 5, Ishihara in view of Kita discloses the claimed invention as applied to claim 1, above.
Ishihara discloses 5. The wiring board as claimed in claim 1, wherein an upper surface of the second interconnect layer is located at a position recessed more toward the first insulating layer than an upper surface of the second insulating layer (Figs. 2C, 3D-4C, [0023], [0031], [0035], [0039], [0046]; an upper surface of the conductor layer 58B1 is located at a position recessed more toward the insulating layer 50A than an upper surface of the insulating layer 50C).
Regarding claim 6, Ishihara in view of Kita discloses the claimed invention as applied to claim 1, above.
Ishihara discloses 6. The wiring board as claimed in claim 1, wherein the opening has an inverted truncated cone shape such that a diameter of the opening that opens at the upper surface of the second insulating layer is larger than a diameter of the bottom surface of the opening formed by the upper surface of the first interconnect layer (Figs. 2C, 3D-4C, [0023], [0031], [0035], [0039], [0046]; the opening has an inverted truncated cone shape such that a diameter of the opening that opens at the an upper surface of the insulating layer 50C is larger than a diameter of the bottom surface of the opening formed by the upper surface of the conductor layer 34).
Regarding claim 8, Ishihara in view of Kita discloses the claimed invention as applied to claim 1, above.
Ishihara discloses 8. The wiring board as claimed in claim 1, wherein the second insulating layer is a solder resist layer (Figs. 2C, 3D-4C, [0023], [0031], [0035], [0039], [0046]; A first solder resist layer can be formed on an uppermost resin insulating layer and an uppermost conductor layer of the printed wiring board 10 of each of the embodiments.).
Regarding claim 9, Ishihara in view of Kita discloses the claimed invention as applied to claim 1, above.
Ishihara does not disclose the limitations of claim 9.
Kita discloses 9. The wiring board as claimed in claim 1, wherein: the second interconnect layer includes an electrolytic plating layer in contact with the seed layer to fill the opening, and an upper surface of the electrolytic plating layer and the end surface of the seed layer are located at positions lower than the upper surface of the second insulating layer to form a recess that is recessed toward the first insulating layer with respect to the upper surface of the second insulating layer (Fig. 1, 5A-C, [0029]-[0033], [0039], [0041], [0051], [0053]; the interconnect layer 42 may be formed by use of electrolytic plating that utilizes the adhesion layer 41 as a power feed layer, an upper surface of the interconnect layer 42 and the end surface of the adhesion layer 41 are located at positions lower than the upper surface of the solder resist layer 50 to form a recess that is recessed toward the first resin layer 11 with respect to the upper surface of the solder resist layer 50).
Regarding claim 10, Ishihara in view of Kita discloses the claimed invention as applied to claim 9, above.
Ishihara does not disclose the limitations of claim 10.
Kita discloses 10. The wiring board as claimed in claim 9, wherein the upper surface of the electrolytic plating layer and the end surface of the seed layer are located on a single plane (Fig. 1, 5A-C, [0029]-[0033], [0039], [0041], [0051]; the upper surface of the interconnect layer 42 and the end surface of the adhesion layer 41 are located on a single plane).
Regarding claim 11, Ishihara in view of Kita discloses the claimed invention as applied to claim 9, above.
Ishihara does not disclose the limitations of claim 11.
Kita discloses 11. The wiring board as claimed in claim 9, wherein a depth of the recess is in a range of approximately 1/3 to approximately 1/2 times a diameter an opening of the recess, the opening of the recess opening at the upper surface of the second insulating layer (Fig. 1, 5A-C, [0029]-[0033], [0039], [0041], [0051]; a depth of the via hole 10x is in a range of approximately 1/3 to approximately 1/2 times a diameter an opening of the recess, the opening of the recess opening at the upper surface of the solder resist layer 50. Examiner’s note: see the 112 rejection above for the construction of this limitation.).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ishihara in view of Kita and “Shin” (US 2020/0205284).
Regarding claim 7, Ishihara discloses 7. The wiring board as claimed in claim 6, wherein: the first interconnect layer includes a via interconnect filling a via hole that penetrates the first insulating layer (Figs. 2C, 3D-4C, [0023], [0031], [0035], [0039], [0046]; the conductor layer 34 includes a via interconnect filling a via hole 36A that penetrates the first insulating layer 50A),
the via hole has an inverted truncated cone shape such that a diameter of the via hole that opens toward the second insulating layer is larger than a diameter of a bottom surface of the via hole formed by an upper surface of a lower interconnect layer (Figs. 2C, 3D-4C, [0023], [0031], [0035], [0039], [0046]; the via hole 36A has an inverted truncated cone shape such that a diameter of the via hole 36A that opens toward the second insulating layer 50C is larger than a diameter of a bottom surface of the via hole 36A formed by an upper surface of a lower interconnect layer 34).
Ishihara does not disclose an angle formed by an inner surface of the opening with respect to the upper surface of the first interconnect layer is larger than an angle formed by an inner surface of the via hole with respect to the upper surface of the lower interconnect layer in a cross sectional view.
Shin discloses an angle formed by an inner surface of the opening with respect to the upper surface of the first interconnect layer is larger than an angle formed by an inner surface of the via hole with respect to the upper surface of the lower interconnect layer in a cross sectional view (Fig. 18, [0120], [0144]; an angle formed by an inner surface of the opening of the via 111C with respect to the upper surface of the first interconnect layer is larger than an angle formed by an inner surface of the via hole 106 with respect to the upper surface of the lower interconnect layer in a cross sectional view).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Ishihara’s wiring board, as modified by Kita, with Shin’s vias in order for the second via hole to include only one pattern groove, and thus a product unit cost may be reduced, as suggested by Shin at [0037].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANLEY TSO whose telephone number is (571)270-0723. The examiner can normally be reached Tu-Thurs 6am-6pm, alt M 6am-2pm.
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/STANLEY TSO/Primary Examiner, Art Unit 2847
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