Prosecution Insights
Last updated: August 17, 2026
Application No. 18/822,954

METHOD FOR SINGULATING A SEMICONDUCTOR COMPONENT HAVING A PN JUNCTION AND SEMICONDUCTOR COMPONENT HAVING A PN JUNCTION

Non-Final OA §112
Filed
Sep 03, 2024
Priority
Sep 24, 2018 — DE 102018123484.8 +2 more
Examiner
PETERSON, ERIK T
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
281 granted / 364 resolved
+9.2% vs TC avg
Moderate +11% lift
Without
With
+11.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
48 currently pending
Career history
408
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
44.2%
+4.2% vs TC avg
§102
20.4%
-19.6% vs TC avg
§112
29.5%
-10.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 364 resolved cases

Office Action

§112
DETAILED ACTION This action is responsive to the application No. 18/822,954 filed on September 3, 2024. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the transverse conduction layer, the semiconductor component having the combination of: (1) an emitter, the pn junction, the separation trench completely passing through the transverse conduction layer and the pn junction, a passivation layer in the separating trench and covering the pn junction, and one or a plurality of metal contact structures; (2) the emitter, the pn junction, the transverse conduction layer in parallel with the emitter and electrically conductively connected thereto, the separation trench completely passing through the transverse conduction layer, and the pn junction, a passivation layer in the separating trench and covering the pn junction, and one or a plurality of metal contact structures; (3) the semiconductor component showing the alternative wherein the separating surface “borders” the transverse conduction avoidance region (as best understood, only the alternative wherein the separating surface passes through the region is shown); (4) the state of the resulting structure according to claim 3 comprising all of the structural features of claim 1; (5) the state of the resulting structure according to claims 6-8 comprising all of the structural features of claim 1; (6) the state of the structure according to Fig. 1B wherein the extended separating trenches are greater than 0 mm from the edge (included in the range of less than 0.3 mm, only a distance of 0 mm is shown), must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-9 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 1 requires the combination of at least the pn junction, the separating trench passing completely through the transverse conduction layer and the pn junction, and the passivation layer covering the pn junction. As best understood, this combination only corresponds to the embodiment shown in Fig. 1B. Claim 1 also recites in lines 10-11, “…and/or b) the transverse conduction layer being formed in parallel with the emitter and being electrically conductively connected thereto…”, apparently drawn to the embodiments shown in Figs. 1D and 1E having the TCO layer 2d1 or 2e1, however none of these embodiments have the pn junction or passivation layer. Thus the claimed combination regarding the limitations following the “or” are not disclosed, nor is there support for all of the claimed elements according to the “and” option in the “and/or” recited in any embodiment. Claim 3, depending from claim 1 (as best understood is drawn to the Fig. 1B embodiment), recites new matter as it is drawn to an unsupported hybrid embodiment, apparently some new combination of Fig. 1B and Figs. 1D-1E. Claim 5 recites the trenches are extended before the semiconductor component is singulated such that ends of the separating trench have a distance of less than 0.3 mm from the edges of the semiconductor component. According to the specification, this step forms trenches to the edge such that A=0 (¶83). The claimed range, including values greater than 0 mm do not have written description support. Only a value of 0 mm appears to have written description support. Claims 6-8, depending from claim 1 (as best understood is drawn to the Fig. 1B embodiment), recite new matter as these claims are drawn to unsupported hybrid embodiments, apparently some new combination(s) of Fig. 1B and Figs. 1C and/or 1E. Further still, there is no written description support for the combination of changing the crystal structure with the counter-diffusion as these are described as alternatives. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites a transverse conduction layer, having no element label and not specifically shown in any figure. It is confusing what Applicant regards as the transverse conduction layer. It is confusing whether Applicant intends for the emitter layer to comprise (e.g. include, in a group) another layer being the transverse conduction layer, or if the emitter layer is the transverse conduction layer. The metes and bounds of “formed in parallel with” are also unclear as this could be understood to mean formed simultaneously, or formed as a layer that is parallel to the surface of the emitter layer. Next, claim 1 recites the separating surface “borders” the transverse conduction avoidance region, while the figures appear to only show the alternative wherein the surface T passes through the region. It is unclear what Applicant intends by “borders” as this alternative is not shown in any figure. The method of claim 3 is unclear as the resulting structure is not shown (elements of claim 1 + claim 3), also see discussion above, the transverse conduction layer is not clear. The structures resulting from the methods of claims 6-8 are unclear as these are drawn to combinations not disclosed or shown. Claim 1 requires the transverse conduction avoidance region to be a trench (i.e. where material is removed) while claims 6-8 require modifying the material properties of this same region (changing crystallinity and doping) that is no longer present (i.e. the trench is empty space, sans material). The combinations do not make sense. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches related devices, having emitter and base layers (not necessarily solar cells), pn junctions, and trenches with passivation. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Sep 03, 2024
Application Filed
Jun 09, 2026
Response after Non-Final Action
Jul 13, 2026
Non-Final Rejection mailed — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
88%
With Interview (+11.2%)
2y 7m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 364 resolved cases by this examiner. Grant probability derived from career allowance rate.

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