DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-20 are pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/3/2024 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 6-8, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 20210202303 A1).
Re Claim 1 Kim teaches a semiconductor package (10) [0070], comprising:
a first wiring structure (300) [0020];
an extension structure (400) [0018] disposed on the first wiring structure (300), the extension structure (400) comprising an extension base layer (411 & 431) [0028 & 0029] and a plurality of via structures (413, 415, 417, 433, & 435) [0028 & 0029], and having a mounting space (space between 411 on left of 100 and 411 on right of 100) passing through the extension base layer (411), wherein the plurality of via structures (413, 415, 417, 433, & 435) comprises a plurality of via connection patterns (413, 417, & 435) disposed on upper and lower surfaces of the extension base layer (411 & 431) and a plurality of extension vias (415 & 433) connecting two via connection patterns (413 & 435), among the plurality of via connection patterns (413, 417, & 435), to each other, the two via connection patterns (413 & 435) being at different vertical levels from one another (FIG. 1);
a semiconductor chip (100) [0018] disposed in the mounting space (space between 411 on left of 100 and 411 on right of 100) and electrically connected to the first wiring structure (300);
a filling insulating layer (500) [0031] filling the mounting space (space between 411 on left of 100 and 411 on right of 100);
a second wiring structure (VS & 600) [0033] disposed on the extension structure (400) and the filling insulating layer (500) and electrically connected to the first wiring structure (300) through the plurality of via structures (413, 415, 417, 433, & 435),
wherein lowermost via connection patterns (413), among the plurality of via connection patterns (413, 417, & 435), comprise a plurality of first lower connection pads (413), and
wherein the extension base layer (411 & 431) comprises base dams (see modified FIG. 1 below) respectively passing through the plurality of first lower connection pads (413) and protruding and extending from the plurality of first lower connection pads (413).
Modified FIG. 1 shown below
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Re Claim 2 Kim teaches the semiconductor package of claim 1, wherein the plurality of first lower connection pads (413) are arranged around the mounting space (space between 411 on left of 100 and 411 on right of 100, FIG. 1).
Re Claim 6 Kim teaches the semiconductor package of claim 1, wherein the base dam (see modified FIG. 1 under claim 1) is disposed between the mounting space (space between 411 on left of 100 and 411 on right of 100) and an extension via (415) connected to each of the plurality of first lower connection pads (413), among the plurality of extension vias (415 and 433, FIG. 1).
Re Claim 7 Kim teaches the semiconductor package of claim 6, wherein the base dam (see modified FIG. 1 under claim 1) at least partially surrounds a region of the extension via (Kim, 415) that is connected to each of the plurality of first lower connection pads (413) facing the mounting space (space between 411 on left of 100 and 411 on right of 100, FIG. 1).
Re Claim 8 Kim teaches the semiconductor package of claim 6, wherein the base dam (see modified FIG. 1 under claim 1) comprises a first base dam (left) and a second base dam (right) which are spaced apart from each other between the mounting space (space between 411 on left of 100 and 411 on right of 100) and the extension via (415) connected to each of the plurality of first lower connection pads (413, FIG. 1).
Re Claim 10 Kim teaches the semiconductor package of claim 1, wherein the lowermost via connection patterns (413), among the plurality of via connection patterns (413, 417, & 435), are buried in the extension base layer (411 & 431), and uppermost via connection patterns (435), among the plurality of via connection patterns (413, 417, & 435), protrude upward from the upper surface of the extension base layer (411 & 431, FIG. 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20210202303 A1) as applied to claims 1 and 2 above, and further in view of Park et al. (US 20200235058 A1).
Re Claim 3 Kim teaches the semiconductor package of claim 2, wherein the extension base layer (411) and the lower surfaces of the lowermost via connection patterns (413), among the plurality of via connection patterns (413, 417, & 435), define a plurality of lower recesses (use regions of 411 material horizontally level with 413, see modified FIG. 1 under claim 1).
Kim does not teach a lower surface of each of the lowermost via connection patterns, among the plurality of via connection patterns, is at a higher vertical level than a lower surface of the extension base layer.
Park teaches a lower surface of each of the lowermost via connection patterns (112a) [0101], among the plurality of via connection patterns (112a-c), is at a higher vertical level than a lower surface of the extension base layer (111a, FIG. 13).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Park into the structure of Kim since Park teaches a semiconductor package structure.
The ordinary artisan would have been motivated to modify Park in combination with Kim in the above manner for the motivation of optimally forming the extension base layer around the lowermost via connection patterns to maintain peak electrical connections in the device. [0005] states, “An aspect of the present disclosure provides a semiconductor package capable of reducing a decrease in reliability caused by cracking in an electrical connection structure and/or around a UBM layer.”
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20210202303 A1) in view of Park et al. (US 20200235058 A1) as applied to claims 1-3 above, and further in view of Lee et al. (US 20210384153 A1).
Re Claim 4 Kim in view of Park teaches the semiconductor package of claim 3, but does not teach the filling insulating layer includes a bleeding portion extending from the mounting space into some of the plurality of lower recesses.
Lee teaches the filling insulating layer (FIG. 10, 400) [0026] includes a bleeding portion extending from the mounting space (area occupied by 300) into some of the plurality of regions under the via connection patterns (233) [0052]. Integrating Lee’s teaching into Kim in view of Park leads to the bleeding portion extending from the mounting space into some of the plurality of lower recesses.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Lee into the structure of Kim in view of Park since Lee teaches a semiconductor package structure.
The ordinary artisan would have been motivated to modify Lee in combination with Kim in view of Park in the above manner for the motivation of optimally forming the filling insulating layer around the mounting space and into some of the plurality of lower recesses to build an optimal FOPLP device as the size of the chip continues to shrink. [0003] states, “As the size of a semiconductor chip has decreased, a semiconductor package has been proposed in which an input/output terminal is placed outside the semiconductor chip by the use of a redistribution layer. For example, a fan-in wafer level package (FIWLP) type semiconductor package, a fan-out wafer level package (FOWLP) type semiconductor package, a fan-out panel level package (FOPLP) type semiconductor package, and the like have been proposed.”
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20210202303 A1) as applied to claim 1 above, and further in view of Lee et al. (KR 20220086284 A).
Re Claim 9 Kim teaches the semiconductor package of claim 1, but does not teach a thickness of the lowermost via connection pattern, among the plurality of via connection patterns, is less than thicknesses of each of the other via connection patterns, among the plurality of via connection patterns
Lee teaches a thickness of the lowermost via connection pattern (top 142d, page 25 par 3, 142D from Lee is similar to 413 of Kim), among the plurality of via connection patterns (142D & 152, page 27 par 2) is less than thicknesses of each of the other via connection patterns (152), among the plurality of via connection patterns (142D & 152, FIG. 13)
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Lee into the structure of Kim since Lee teaches a semiconductor package structure.
The ordinary artisan would have been motivated to modify Lee in combination with Kim in view of Park in the above manner for the motivation of forming the via connection patterns to be the optimal thickness as semiconductor device continue to become thinner. Page 3 last par states, “As semiconductor devices become thinner and stacked for integration, interest in stacking means and stacking processes of semiconductor devices is increasing.”
Claims 11, 15-16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (KR 20220022602 A) in view of Park et al. (US 20180076178 A1).
Re Claim 11 Kim teaches a semiconductor package (300A, page 11 par 8, FIG. 8), comprising:
a first wiring structure (140, page 6 par 1);
a second wiring structure (170, page 7 par 6) disposed above the first wiring structure (140);
an extension structure (110, page 7 last par) disposed between the first wiring structure (140) and the second wiring structure (170) and having a mounting space (region between 110 sections) passing through the extension structure (110) from an upper surface to a lower surface thereof (FIG. 8);
a semiconductor chip (120, page 5 last par) disposed inside the mounting space (region between 110 sections); and
a filling insulating layer (130, page 5 last par) filling the mounting space (region between 110 sections) and covering the upper surface of the semiconductor chip (120) and an upper surface of the extension structure (110),
wherein the extension structure (110) comprises a plurality of extension base layers (111a-b, page 4 par 1) stacked on each other, a plurality of via connection patterns (112a-c) disposed on the upper and lower surfaces of each of the plurality of extension base layers (111a-b), and a plurality of extension vias (113a-b) passing through at least one extension base layer (111a), among the plurality of extension base layers (111a-b), and connecting two via connection patterns (112a and 112c), among the plurality of via connection patterns (112a-c), to each other which are at different vertical levels from one another (FIG. 8),
wherein lowermost via connection patterns (112a), among the plurality of via connection patterns (112a-c), comprise a plurality of first lower connection pads (inner 112a) arranged around the mounting space (region between 110 sections) and a plurality of second lower connection pads (outer 112a) at least partially surrounding the plurality of first lower connection pads (see modified FIG. 8 below).
Modified FIG. 8 shown below
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Kim does not teach the lowermost via connection patterns, among the plurality of via connection patterns each having a pad trench,
wherein the extension base layer comprises a base dam which passes through each of the plurality of first lower connection pads while filling the pad trench, and protrudes downward from a lower surface of each of the plurality of first lower connection pads.
Park teaches the lowermost via connection patterns (112a) [0098], among the plurality of via connection patterns (112a-c) each having a pad trench (gap in 112a, FIG. 11),
wherein the extension base layer (111a) comprises a base dam (111a between 112a and lower than 112a) which passes through each of the plurality of first lower connection pads (112a) while filling the pad trench (gap in 112a), and protrudes downward from a lower surface of each of the plurality of first lower connection pads (112a, FIG. 11).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Park into the structure of Kim since Park teaches a semiconductor package structure.
The ordinary artisan would have been motivated to modify Park in combination with Kim in the above manner for the motivation of optimally forming the lower via connection patterns to build a device that functions at a peak level and is still as small as possible. [0003] states, “Recently, a significant recent trend in the development of semiconductor chip-related technology has been reducing the size of semiconductor chips.”
Re Claim 15 Kim in view of Park teaches the semiconductor package of claim 11, wherein the plurality of first lower connection pads (Kim, inner 112a) and the plurality of second lower connection pads (outer 112a) are buried in a lowermost extension base layer (111a) among the plurality of extension base layers (111a-b, FIG. 8).
Kim in view of Park does not explicitly teach each of the lower connection pads have a lower surface at a vertical level that is higher than a bottom of the lowermost extension base layer.
Park does teach the lower connection pads (112a, 2 total) have a lower surface at a vertical level that is higher than a bottom of the lowermost extension base layer (111a, FIG. 11). Integrating Park’s teachings into Kim in view of Park leads to each of the lower connection pads having a lower surface at a vertical level that is higher than a bottom of the lowermost extension base layer.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Park into the structure of Kim in view of Park.
The ordinary artisan would have been motivated to modify Park in combination with Kim in view of Park in the above manner for the motivation of optimally forming the lower via connection patterns in the extension base layer to build a device that functions at a peak level and is still as small as possible. [0003] states, “Recently, a significant recent trend in the development of semiconductor chip-related technology has been reducing the size of semiconductor chips.”
Re Claim 16 Kim in view of Park teaches the semiconductor package of claim 15, wherein via connection patterns (Ki, 112b), which are at vertical levels higher than the lowermost via connection patterns (112a) and lower than uppermost via connection patterns (112c) among the plurality of via connection patterns (112a-c), have lower surfaces at the same vertical level and are buried in any one of the plurality of extension base layers (111b, FIG. 8).
Re Claim 18 Kim teaches a semiconductor package (300A, page 11 par 8, FIG. 8), comprising:
a first wiring structure (140, page 6 par 1) comprising a first redistribution insulating layer (141), a plurality of first redistribution line patterns (142) disposed on at least one of upper and lower surfaces of the first redistribution insulating layer (141), and a plurality of first redistribution vias (143) passing through the first redistribution insulating layer (141) and respectively connected to some of the plurality of first redistribution line patterns (142);
an extension structure (110, page 6 par 1) disposed on the first wiring structure (140), the extension structure (110) comprising a plurality of extension base layers (111a-b, page 4 par 1) and a plurality of via structures (112a-c & 113a-b) passing through the plurality of extension base layers (111a-b) and (electrically) connected to some of the plurality of first redistribution vias (143), and having a mounting space (region between 110 sections) passing through the plurality of extension base layers (11a-b);
a semiconductor chip (120, page 4 par 2) disposed in the mounting space (region between 110 sections) and comprising a plurality of chip pads (120P, page 4 last par) connected to the others of the plurality of first redistribution vias (143);
a filling insulating layer (130, page 4 par 1) filling the mounting space (region between 110 sections) and covering an upper surface of the semiconductor chip (120) and an upper surface of the extension structure (110); and
a second wiring structure (170 & 180, page 8 par 1 & 2) disposed on the filling insulating layer (130) and comprising a second redistribution insulating layer (180), a plurality of second redistribution line patterns (173) disposed on at least one of the upper and lower surfaces of the second redistribution insulating layer (180), and a plurality of second redistribution vias (171) passing through the second redistribution insulating layer (180) and respectively connected to some of the plurality of second redistribution line patterns (173), the second wiring structure (170 & 180) being electrically connected to the first wiring structure (140) through the plurality of via structures (112a-c & 113a-b),
wherein the plurality of via structures (112a-c & 113a-b) comprises a plurality of via connection patterns (112a-c) disposed on upper and lower surfaces of each of the plurality of extension base layers (111a-b) and a plurality of extension vias (113a-b) passing through at least one extension base layer (111a) and connecting two via connection patterns (112a-b), among the plurality of via connection patterns (112a-c), to each other, the two via connection patterns (112a-b) being at different vertical levels from one another (FIG. 8),
wherein lowermost via connection patterns (112a), among the plurality of via connection patterns (112a-c), are buried in a lowermost extension base layer (111a), among the plurality of extension base layers (111a-b), and comprise a plurality of first lower connection pads (inner 112a) arranged around the mounting space (region between 110 sections) and a plurality of second lower connection pads (outer 112a) at least partially surrounding the plurality of first lower connection pads (see modified FIG. 8 under claim 11).
Kim does not teach the first lower connection pads each having a pad trench, and
wherein the extension base layer comprises a base dam which passes through each of the plurality of first lower connection pads while filling the pad trench and extends into the first redistribution insulating layer.
Park teaches the first lower connection pads (112a) [0098] each having a pad trench (gap in 112a, FIG. 11), and
wherein the extension base layer (111a) [0098] comprises a base dam (111a between 112a and lower than 112a) which passes through each of the plurality of first lower connection pads (111a) while filling the pad trench (gap in 112a, FIG. 11) and extends into the first redistribution insulating layer (141, [0077], FIG. 11).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Park into the structure of Kim since Park teaches a semiconductor package structure.
The ordinary artisan would have been motivated to modify Park in combination with Kim in the above manner for the motivation of optimally forming the lower via connection patterns to build a device that functions at a peak level and is still as small as possible. [0003] states, “Recently, a significant recent trend in the development of semiconductor chip-related technology has been reducing the size of semiconductor chips.”
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (KR 20220022602 A) in view of Park et al. (US 20180076178 A1) as applied to claim 11 above, and further in view of Sailer et al (US 20230215795 A1).
Kim in view of Park teaches the semiconductor package of claim 11, but does not teach each of the plurality of first lower connection pads has a shape in which a first portion having a semicircular shape and a second portion having a rectangular shape are coupled to each other.
Sailer teaches each of the plurality of first lower connection pads (112b, FIG. 3) [0039] has a shape in which a first portion (right side of 112b which is a semicircle) having a semicircular shape and a second portion (center portion of 112b in FIG. 3 with parallel lines on top and bottom) having a rectangular shape are coupled to each other (112b, FIG. 3 & 14, use top 112b in FIG. 14).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Sailer into the structure of Kim in view of Park teaches a semiconductor package structure.
The ordinary artisan would have been motivated to modify Sailer in combination with Kim in view of Park in the above manner for the motivation of optimally shaping the first lower connection pads to provide improved mechanical reliability. [0039] states, “As discussed herein, the larger interconnection members 112b can provide improved mechanical reliability, such as during mechanical shock testing (e.g., drop testing) or during use.”
Kim in view of Park and Sailer does not explicitly teach the pad trench is disposed in the second portion of each of the plurality of first lower connection pads.
Kim in view of Park and Sailer does teach the pad trench (Park, gap in 112a, FIG. 11) is disposed in the center region of each of the plurality of first lower connection pads. Integrating Sailer’s teaching into Park’s structure leads to the pad trench being in the second portion of the first lower connection pads (Sailer, 112b, FIG. 3)
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Sailer into the structure of Kim in view of Park and Sailer.
The ordinary artisan would have been motivated to modify Sailer in combination with Kim in view of Park and Sailer in the above manner for the motivation of optimally forming the first lower connection pads to provide improved mechanical reliability. [0039] states, “As discussed herein, the larger interconnection members 112b can provide improved mechanical reliability, such as during mechanical shock testing (e.g., drop testing) or during use.”
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (KR 20220022602 A) in view of Park et al. (US 20180076178 A1) and Sailer et al (US 20230215795 A1) as applied to claims 11 and 12, and further in view of Bae et al. (KR 20210094329 A).
Kim in view of Park and Sailer teaches the semiconductor package of claim 12, but does not teach each of the pad trench and the base dam has an arc shape.
Bae teaches each of the pad trench (220G, page 8 par 4) and the base dam (pad trench and base dam as taught by Park, gap in 112a for pad trench in FIG. 11 and 111a between 112a and lower than 112a for base dam occupy same vertical space, so use 220G from Bae for pad trench and base dam) has an arc shape (FIG. 5a & 5b).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Bae into the structure of Kim in view of Park and Sailer.
The ordinary artisan would have been motivated to modify Bae in combination with Kim in view of Park and Sailer in the above manner for the motivation of optimally forming the pad trench and base dam as the industry continues to demand smaller chips. Page 3 par 2 states, “According to the rapid development of the electronic industry and the needs of users, electronic devices are becoming smaller, more multifunctional, and larger in capacity, and accordingly, a highly integrated semiconductor chip is required.”
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (KR 20220022602 A) in view of Park et al. (US 20180076178 A1) as applied to claim 11 above, and further in view of Lee et al. (US 20210384153 A1).
Re Claim 17 Kim in view of Park teaches the semiconductor package of claim 11, but does not teach the filling insulating layer comprises a bleeding portion that extends from the mounting space along the lower surface of the extension structure and contacts the lower surface of at least one of the plurality of first lower connection pads.
Lee teaches the filling insulating layer (FIG. 10, 400) [0026] comprises a bleeding portion that extends from the mounting space (area occupied by 300) along the lower surface of the extension structure (200) [0026] and contacts the lower surface of at least one of the plurality of first lower connection pads (233) [0052].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Lee into the structure of Kim in view of Park since Lee teaches a semiconductor package structure.
The ordinary artisan would have been motivated to modify Lee in combination with Kim in view of Park in the above manner for the motivation of optimally forming the filling insulating layer around the mounting space and along the extension structure to build an optimal FOPLP device as the size of the chip continues to shrink. [0003] states, “As the size of a semiconductor chip has decreased, a semiconductor package has been proposed in which an input/output terminal is placed outside the semiconductor chip by the use of a redistribution layer. For example, a fan-in wafer level package (FIWLP) type semiconductor package, a fan-out wafer level package (FOWLP) type semiconductor package, a fan-out panel level package (FOPLP) type semiconductor package, and the like have been proposed.”
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (KR 20220022602 A) in view of Park et al. (US 20180076178 A1) as applied to claim 18 above, and further in view of Park et al. (US 20200235058 A1, “Park2” hereafter)
Re Claim 19 Kim in view of Park teaches the semiconductor package of claim 18, but does not teach each of the plurality of first lower connection pads and the plurality of second lower connection pads has a lower surface at a vertical level that is higher than a bottom of the lowermost extension base layer by about 2 μm to about 5 μm.
Park2 [0093] states, “…redistribution pattern 142 may be about 0.5 μm to 15 μm.” Lower connection pads (112a) [0101] have a lower surface at a vertical level that is higher than a bottom of the lowermost extension base layer (111a) by about the same distance 142 is thick. Therefore, lower connection pads have a lower surface at a vertical level that is higher than a bottom of the lowermost extension base layer by about 0.5 μm to 15 μm.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Park2 into the structure of Kim in view of Park since Park2 teaches a semiconductor package structure.
The ordinary artisan would have been motivated to modify Park2 in combination with Kim in view of Park in the above manner for the motivation of finding the ideal distance between the bottom of the lowermost extension base layer and the lower connection pads’ lower surface at a vertical level. [0005] states, “An aspect of the present disclosure provides a semiconductor package capable of reducing a decrease in reliability caused by cracking in an electrical connection structure and/or around a UBM layer.” Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach optimal spacing between the bottom of the connection pads and the bottom most surface of the lowermost extension base layer.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (KR 20220022602 A) in view of Park et al. (US 20180076178 A1) as applied to claim 18 above, and further in view of Marin et al. (US 20200083164 A1).
Re Claim 20 Kim in view of Park teaches the semiconductor package of claim 18, wherein the base dam (Park, 111a between 112a and lower than 112a) is disposed between the mounting space (space occupied by 120 and 130, [0062], FIG. 11) and an extension via (113a) [0098] connected to each of the plurality of first lower connection pads (112a), among the plurality of extension vias (113a-b).
Kim in view of Park does not teach the base dam extends with a horizontal width of about 10 μm to about 30 μm to at least partially surround a region of the extension via facing the mounting space.
Marin [0068] states, “…via pads 321 may have a diameter of approximately between 5 μm to 50 μm.” Integrating Marin’s teaching into Park for via connection patterns (112a) and considering Park base dam (111a between 112a and lower than 112a, FIG. 11) is about one fourth of the total length of 112a leads one to conclude the base dam is about 1.25 μm to about 12.5 μm, and Park FIG. 11 shows the base dam (111a between 112a and lower than 112a) at least partially surround a region of the extension via (113a) facing the mounting space (space occupied by 120 and 130, [0062], FIG. 11).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Park2 into the structure of Kim in view of Park since Marin teaches a semiconductor package structure.
The ordinary artisan would have been motivated to modify Marin in combination with Kim in view of Park in the above manner for the motivation of finding the ideal base dam horizontal width. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach optimal base dam horizontal width.
Allowable Subject Matter
Claims 5 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Jeon et al. (CN 107808860 A) teaches a semiconductor package comprising an extension structure and a semiconductor chip mounting space over a wiring structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH MARK SIPLING/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 9/23/26
Prosecution Insights