DETAILED ACTION
Response to Amendment
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Hiraishi (U.S. Patent Application Publication Number 2019/0371388), Kim et al. (U.S. Patent Application Publication Number 2019/0287587), and Choe (U.S. Patent Application Publication Number 2021/0165587).
Regarding Claim 1, Hiraishi discloses a write training circuit (Figure 1, item 18, paragraphs 0020-0021; i.e., the calibration procedure described in the reference is equivalent to the claimed write training because it involves adjusting timing delays and voltage levels to receive the data correctly) comprising:
a data receiving circuit (Figure 1, item 19) configured to receive data input (Figure 1, item DQ[7:0]) according to a plurality of multi-phase clock signals (Figure 1, items DQS1-DQS4) to generate received data (Figure 2, paragraph 0018; i.e., the receiver replica circuit 44 is a replica of the data DQ receiver 19; both of these circuits latch the incoming data at the designated strobe timing points, which are based on the multi-phase DQS signals);
a strobe signal processing circuit (Figure 1, item 21) configured to generate the plurality of multi-phase clock signals by dividing a data strobe signal (Figure 1, item DQS_t and DQS_c) into divided signals (Figure 1, item 22) and delaying (Figure 1, item 23) the divided signals by a predetermined time period (paragraphs 0017 and 0019; i.e., the incoming data strobe signal is divided into four-phase strobe signals DQS1-DQS4, which can further be delayed by a predetermined time period determined by delay circuit 23).
Hiraishi does not expressly disclose a skew detection circuit configured to generate a replication clock signal corresponding to one of the plurality of multi-phase clock signals and configured to generate skew information according to the replication clock signal;
wherein the skew detection circuit is configured to generate the skew information under external control or independently of external control depending on which of a plurality of external commands is received.
In the same field of endeavor (e.g., memory training techniques), Kim teaches a skew detection circuit (Figure 3, item 400, paragraph 0053) configured to generate (Figure 3, item 410, paragraph 0054) a replication clock signal (Figure 3, item DQS_re, paragraph 0053) corresponding to a clock signal (paragraph 0053; i.e., a replica of a data strobe clock signal [see Figure 4, item DQS_CLK]) and configured to generate skew information (Figure 3, item D_CODE, paragraph 0051) according to the replication clock signal (paragraph 0053; i.e., the sampler 330 will only output the rising and falling data R_DATA and F_DATA [which are used by the skew controller 420 to generate the skew information D_CODE] when it receives the delay data strobe clock D_DQSB; the DQS CLK Output Circuit 350 will only output the delay data strobe clock D_DQSB when it receives the replica clock signal DQS_re from CLK generator 410; accordingly, the skew information D_CODE is generated "according to the replication clock signal" DQS_re).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Kim’s teachings of memory training techniques with the teachings of Hiraishi, for the purpose of eliminating the skew between the strobe signal and the data signal, thereby having more accurate sampling of the data.
Also in the same field of endeavor (e.g., memory training techniques), Choe teaches wherein the skew detection circuit (Figure 1, item 121) is configured to generate the skew information (paragraph 0023; i.e., the delay selection signal DELAY_SEL) under external control or independently of external control depending on which of a plurality of external commands (paragraph 0021; i.e., the memory medium 110 can receive a plurality of external commands including a read command, write command, and command to transmit the data strobe signal to the memory controller 120 for training) is received (paragraphs 0023-0024; i.e., the skew detection circuit 121 generates the skew information independent of external control when the memory module 110 receives the command to transmit the data strobe signal to the memory controller 120 for training).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Choe’s teachings of memory training techniques with the teachings of Hiraishi, for the purpose of providing added control to the skew detection. More specifically, it would allow the controller to perform the skew correction only at times when it desires to (e.g., when it is idle).
Regarding Claim 2, Choe teaches wherein the skew detection circuit is configured to output the skew information to an external device in response to external control (paragraph 0020; i.e., skew information is provided to the memory [which is “external” to the memory controller] that adjusts the phase [to correct for skew] by training the memory, which occurs based on external training instructions from the memory controller).
Regarding Claim 3, Kim teaches wherein the skew detection circuit comprises a strobe signal replication circuit (Figure 4, item 411) configured to generate the replication clock signal during a time period during which an oscillation enable signal is active (Figure 4, item ST_S, paragraph 0055);
a counter configured to generate the skew information by counting edges of the replication clock signal during the time period during which the oscillation enable signal is active (paragraph 0088; i.e., the timer TM [equivalent to the claimed “counter”], which is a part of the skew controller 420 that generates the skew information D_CODE, counts the rising and falling edges R_DATA and F_DATA and the number of edges of the common clock CLKcom; the common clock CLKcom and the replication clock DQS_re are the same [see paragraph 0094]); and
a timing control circuit (Figure 3, item 420) configured to generate the oscillation enable signal in response to a plurality of timing control signals (Figure 3, items PDLPF, VAL, and AMB, paragraph 0055).
Regarding Claim 4, Choe teaches wherein the plurality of timing control signals (e.g., data strobe signals, which are used to control timing of data transmitted by the memory controller 120) are generated by decoding the plurality of external commands (paragraph 0021; i.e., the examiner takes Official Notice that decoding of commands in a memory device, e.g., through the use of a command decoder, is well known in the art for the purpose of being able to properly interpret the received commands as evidenced by Park et al. [U.S. Patent Application Publication Number 2020/0058336 [see paragraph 0032]).
Regarding Claim 5, Hiraishi discloses a deserialization circuit that deserializes the received data according to at least one of the plurality of multi-phase clock signals (claim 5; i.e., the data is received in parallel [deserialized] based on the multi-phase strobe signals).
Claims 6, 7, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Hiraishi and Mizumoto et al. (U.S. Patent Application Publication Number 2019/0004983).
Regarding Claim 6, Hiraishi discloses a semiconductor device (Figure 1, item 12) comprising:
a semiconductor memory apparatus (paragraph 0016) configured to perform a normal operation when a command for the normal operation is received (paragraphs 0003 and 0022; i.e., a command to write or read data to the memory) and configured to perform a write training operation (Figure 1, item 18, paragraphs 0020-0021; i.e., the calibration procedure described in the reference is equivalent to the claimed write training because it involves adjusting timing delays and voltage levels to receive the data correctly);
wherein the write training operation comprises internally multi-phase processing (paragraphs 0017 and 0019; i.e., the incoming data strobe signal is divided into four-phase strobe signals DQS1-DQS4) a data strobe signal (Figure 1, item DQS_t and DQS_c) provided from an external device (Figure 1, item 11) to detect a time to latch data (Figure 1, item DQ[7:0]) provided from the external device (Figure 2, paragraph 0018; i.e., the receiver replica circuit 44 is a replica of the data DQ receiver 19; both of these circuits latch the incoming data at the designated strobe timing points, which are based on the multi-phase DQS signals).
Hiraishi does not expressly disclose performing the write training operation during a time period during which the normal operation is performed;
wherein the normal operation includes a program operation.
In the same field of endeavor (e.g., memory training techniques), Mizumoto teaches performing the write training operation during a time period during which the normal operation is performed (Figure 5, “WT Phase” and “Normal Control”, paragraphs 0071 and 0076; i.e., the master A 20 is allowed to perform a normal operation such as a write while the write training is occurring);
wherein the normal operation includes a program operation (paragraphs 0020 and 0071; i.e., in the period of the write training, the central bus-control system 50 grants the access right only in response to the write request issued by the master A 20, in which the real-time property needs to be ensured; this "real-time property" corresponds to "normal" processing such as image display and video input).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Mizumoto’s teachings of memory training techniques with the teachings of Hiraishi, for the purpose of improving the response to the write request so as to ensure a real-time property (see Mizumoto, paragraph 0080).
Regarding Claim 7, Mizumoto teaches wherein the normal operation further includes a normal data output operation (Figure 5, “WT Phase” and “Normal Control”, paragraphs 0071 and 0076; i.e., the master A 20 is allowed to perform a normal data output operation such as a write while the write training is occurring) and an erase operation (paragraph 0103; i.e., a write request can be deleted/erased).
Regarding Claim 14, Hiraishi discloses a deserialization circuit that deserializes the received data according to at least one of the plurality of multi-phase clock signals (claim 5; i.e., the data is received in parallel [deserialized] based on the multi-phase strobe signals).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Hiraishi and Mizumoto as applied to claim 6 above, and further in view of Choe.
Regarding Claim 8, Hiraishi and Mizumoto do not expressly disclose wherein the write training operation is performed under external control or independently of external control depending on which of a plurality of external commands is received.
In the same field of endeavor (e.g., memory training techniques), Choe teaches wherein the write training operation is performed under external control or independently of external control depending on which of a plurality of external commands (paragraph 0021; i.e., the memory medium 110 can receive a plurality of external commands including a read command, write command, and command to transmit the data strobe signal to the memory controller 120 for training) is received (paragraphs 0023-0024; i.e., the skew detection circuit 121 generates the skew information independent of external control when the memory module 110 receives the command to transmit the data strobe signal to the memory controller 120 for training).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Choe’s teachings of memory training techniques with the teachings of Hiraishi and Mizumoto, for the purpose of providing added control to the skew detection. More specifically, it would allow the controller to perform the skew correction only at times when it desires to (e.g., when it is idle).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Hiraishi and Mizumoto as applied to claim 6 above, and further in view of Park et al. (U.S. Patent Application Publication Number 2020/0058336).
Regarding Claim 9, Hiraishi and Mizumoto do not expressly disclose wherein the semiconductor device is further configured to perform a preparation operation for the write training operation for a corresponding logic unit when a write training enable command is received from the external device; initiate an operation that generates skew information when a write training start command is received from the external device; stop the operation that generates the skew information when a write training stop command is received from the external device; and provide the skew information to the external device when a skew information acquisition command is received from the external device.
In the same field of endeavor (e.g., memory training techniques), Park teaches wherein the semiconductor device is further configured to perform a preparation operation for the write training operation for a corresponding logic unit when a write training enable command is received from the external device (paragraph 0025; i.e., activating the selected training mode); initiate an operation that generates skew information when a write training start command is received from the external device (Figure 1, item 1, paragraph 0026); stop the operation that generates the skew information when a write training stop command is received from the external device (paragraph 0049); and provide the skew information to the external device when a skew information acquisition command is received from the external device (paragraphs 0036-0037 and 0047; i.e., the memory device 3 supplies the “skew information” TDATA to the controller 1 upon receiving a command to do so).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Park’s teachings of memory training techniques with the teachings of Hiraishi and Mizumoto, for the purpose of ensuring that the data transmission is synchronized between the memory controller and the memory device (i.e., the purpose of adjusting a data strobe signal based on skew information).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Hiraishi and Mizumoto as applied to claim 6 above, and further in view of Choe and Kim.
Regarding Claim 10, Hiraishi and Mizumoto do not expressly disclose wherein the semiconductor memory apparatus is configured to perform a preparation operation for the write training operation for a corresponding logic unit when a write training enable command is received from the external device and configured to perform starting and stopping of a skew information generation operation independently of external control for a predetermined time period.
In the same field of endeavor (e.g., memory training techniques), Choe teaches wherein the semiconductor memory apparatus is configured to perform a preparation operation for the write training operation for a corresponding logic unit when a write training enable command is received from the external device (paragraphs 0023-0024; i.e., when the memory controller 120 commands the memory device 110 to transmit the data strobe signal, the memory controller 120 must first generate the data strobe signal [the claimed “preparation operation”]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Choe’s teachings of memory training techniques with the teachings of Hiraishi and Mizumoto, for the purpose of providing added control to the skew detection. More specifically, it would allow the controller to perform the skew correction only at times when it desires to (e.g., when it is idle).
Also in the same field of endeavor (e.g., memory training techniques), Kim teaches the semiconductor memory apparatus is configured to perform starting and stopping of a skew information generation operation independently of external control for a predetermined time period (paragraph 0069; i.e., the skew information starts based on the ST_S signal and stops based on a LOCK_S signal, which occurs when the skew is corrected [the “predetermined time period”]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Kim’s teachings of memory training techniques with the teachings of Hiraishi and Mizumoto, for the purpose of eliminating the skew between the strobe signal and the data signal, thereby having more accurate sampling of the data.
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Hiraishi and Mizumoto as applied to claim 6 above, and further in view of Kim.
Regarding Claim 11, Hiraishi discloses a data receiving circuit (Figure 1, item 19) configured to receive the data input (Figure 1, item DQ[7:0]) according to a plurality of multi-phase clock signals (Figure 1, items DQS1-DQS4) to generate received data (Figure 2, paragraph 0018; i.e., the receiver replica circuit 44 is a replica of the data DQ receiver 19; both of these circuits latch the incoming data at the designated strobe timing points, which are based on the multi-phase DQS signals);
a strobe signal processing circuit (Figure 1, item 21) configured to generate the plurality of multi-phase clock signals by dividing the data strobe signal (Figure 1, item DQS_t and DQS_c) into divided signals (Figure 1, item 22) and delaying (Figure 1, item 23) the divided signals by a predetermined time period (paragraphs 0017 and 0019; i.e., the incoming data strobe signal is divided into four-phase strobe signals DQS1-DQS4, which can further be delayed by a predetermined time period determined by delay circuit 23).
Hiraishi and Mizumoto do not expressly disclose a skew detection circuit configured to generate a replication clock signal corresponding to one of the plurality of multi-phase clock signals according to one of a plurality of external commands and configured to generate skew information according to the replication clock signal.
In the same field of endeavor (e.g., memory training techniques), Kim teaches a skew detection circuit (Figure 3, item 400, paragraph 0053) configured to generate (Figure 3, item 410, paragraph 0054) a replication clock signal (Figure 3, item DQS_re, paragraph 0053) corresponding to a clock signal (paragraph 0053; i.e., a replica of a data strobe clock signal [see Figure 4, item DQS_CLK]) according to one of a plurality of external commands (Figure 3, item RESET, paragraph 0055) and configured to generate skew information according to the replication clock signal (paragraph 0053; i.e., the skew information D_CODE is generated based on the generated replication clock signal DQS_re).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Kim’s teachings of memory training techniques with the teachings of Hiraishi and Mizumoto, for the purpose of eliminating the skew between the strobe signal and the data signal, thereby having more accurate sampling of the data.
Regarding Claim 12, Kim teaches wherein the skew detection circuit comprises a strobe signal replication circuit configured to generate the replication clock signal during a time period during which an oscillation enable signal is active (Figure 4, item ST_S, paragraph 0055);
a counter configured to generate the skew information by counting edges of the replication clock signal during the time period during which the oscillation enable signal is active (paragraph 0088); and
a timing control circuit (Figure 3, item 420) configured to generate the oscillation enable signal in response to a plurality of timing control signals (Figure 3, items PDLPF, VAL, and AMB, paragraph 0055).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Hiraishi, Mizumoto, and Kim as applied to claim 12 above, and further in view of Park.
Regarding Claim 13, Hiraishi, Mizumoto, and Kim do not expressly disclose wherein the plurality of timing control signals are generated by decoding the plurality of external commands.
In the same field of endeavor (e.g., memory training techniques), Park teaches wherein the plurality of timing control signals (Figure 2, items MRWS and WT) are generated by decoding the plurality of external commands (Figure 2, item 321, paragraph 0032).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Park’s teachings of memory training techniques with the teachings of Hiraishi, Mizumoto, and Kim, for the purpose of being able to properly interpret the received commands.
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Hiraishi, Mizumoto, and Park.
Regarding Claim 15, Hiraishi discloses a data processing system (Figure 1, item 10) comprising:
a semiconductor memory apparatus (Figure 1, item 12) configured to perform a write training operation (Figure 1, item 18, paragraphs 0020-0021; i.e., the calibration procedure described in the reference is equivalent to the claimed write training because it involves adjusting timing delays and voltage levels to receive the data correctly) including detecting a time to latch data (Figure 1, item DQ[7:0]) according to a plurality of multi-phase clock signals (Figure 2, paragraph 0018; i.e., the receiver replica circuit 44 is a replica of the data DQ receiver 19; both of these circuits latch the incoming data at the designated strobe timing points, which are based on the multi-phase DQS signals) that are internally generated (paragraphs 0017 and 0019; i.e., the incoming data strobe signal is divided into four-phase strobe signals DQS1-DQS4, which can further be delayed by a predetermined time period determined by delay circuit 23) based on a data strobe signal (Figure 1, item DQS_t and DQS_c);
a controller (Figure 1, item 11) configured to provide a plurality of commands (paragraphs 0003 and 0022; i.e., commands to write or read data to the memory), the data, and the data strobe signal to the semiconductor memory apparatus (paragraphs 0016-0017).
Hiraishi does not expressly disclose performing the write training operation during a time period during which a normal operation is performed and outputting the time as skew information, configured to perform the write training operation under external control when a write training enable command is received, and configured to perform the write training operation independently of external control when a write training internal processing enable command is received;
wherein the plurality of commands received from the controller include the write training enable command and the write training internal processing enable command; and
the controller is configured to adjust timing of the data strobe signal according to the skew information;
wherein the normal operation includes a program operation.
In the same field of endeavor (e.g., memory training techniques), Mizumoto teaches performing the write training operation during a time period during which the normal operation is performed (Figure 5, “WT Phase” and “Normal Control”, paragraphs 0071 and 0076; i.e., the master A 20 is allowed to perform a normal operation such as a write while the write training is occurring);
wherein the normal operation includes a program operation (paragraphs 0020 and 0071; i.e., in the period of the write training, the central bus-control system 50 grants the access right only in response to the write request issued by the master A 20, in which the real-time property needs to be ensured; this "real-time property" corresponds to "normal" processing such as image display and video input).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Mizumoto’s teachings of memory training techniques with the teachings of Hiraishi, for the purpose of improving the response to the write request so as to ensure a real-time property (see Mizumoto, paragraph 0080).
Also in the same field of endeavor (e.g., memory training techniques), Park teaches outputting the time as skew information (paragraph 0026), configured to perform the write training operation under external control when a write training enable command is received, and configured to perform the write training operation independently of external control when a write training internal processing enable command is received (paragraphs 0025-0026 and 0047; i.e., an external write level training mode or an internal write leveling training mode may be entered based on command received from the controller 1);
wherein the plurality of commands received from the controller (Figure 1, item 1) include the write training enable command and the write training internal processing enable command (paragraphs 0029, 0032-0033, and 0036; i.e., the signal WMEN that controls whether the memory device will operate in the external write level training mode or an internal write leveling training mode occurs based on different information in a command signal CA received from the controller 1); and
the controller is configured to adjust timing of the data strobe signal according to the skew information (paragraphs 0023, 0037, and 0047; i.e., the delay of the data strobe signals DQS_t and DQS_c is adjusted based on the “skew information” TDATA).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Park’s teachings of memory training techniques with the teachings of Hiraishi, for the purpose of ensuring that the data transmission is synchronized between the memory controller and the memory device (i.e., the purpose of adjusting a data strobe signal based on skew information).
Regarding Claim 16, Mizumoto teaches wherein the normal operation further includes a normal data output operation (Figure 5, “WT Phase” and “Normal Control”, paragraphs 0071 and 0076; i.e., the master A 20 is allowed to perform a normal data output operation such as a write while the write training is occurring) and an erase operation (paragraph 0103; i.e., a write request can be deleted/erased).
Regarding Claim 17, Park teaches wherein the semiconductor device is further configured to perform a preparation operation for the write training operation for a corresponding logic unit when a write training enable command is received from the external device (paragraph 0025; i.e., activating the selected training mode); initiate an operation that generates skew information when a write training start command is received from the controller (Figure 1, item 1, paragraph 0026); stop the operation that generates the skew information when a write training stop command is received from the external device (paragraph 0049); and provide the skew information to the external device when a skew information acquisition command is received from the controller (paragraphs 0036-0037 and 0047; i.e., the memory device 3 supplies the “skew information” TDATA to the controller 1 upon receiving a command to do so).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Hiraishi and Mizumoto as applied to claim 15 above, and further in view of Choe and Kim.
Regarding Claim 18, Hiraishi and Mizumoto do not expressly disclose wherein the semiconductor memory apparatus is configured to perform a preparation operation for the write training operation for a corresponding logic unit when a write training enable command is received from the controller and configured to perform, independently of control by the controller, starting and stopping of a skew information generation operation independently of external control for a predetermined time period.
In the same field of endeavor (e.g., memory training techniques), Choe teaches wherein the semiconductor memory apparatus is configured to perform a preparation operation for the write training operation for a corresponding logic unit when a write training enable command is received from the controller (paragraphs 0023-0024; i.e., when the memory controller 120 commands the memory device 110 to transmit the data strobe signal, the memory controller 120 must first generate the data strobe signal [the claimed “preparation operation”]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Choe’s teachings of memory training techniques with the teachings of Hiraishi and Mizumoto, for the purpose of providing added control to the skew detection. More specifically, it would allow the controller to perform the skew correction only at times when it desires to (e.g., when it is idle).
Also in the same field of endeavor (e.g., memory training techniques), Kim teaches the semiconductor memory apparatus is configured to perform, independently of control by the controller, starting and stopping of a skew information generation operation independently of external control for a predetermined time period (paragraph 0069; i.e., the skew information starts based on the ST_S signal and stops based on a LOCK_S signal, which occurs when the skew is corrected [the “predetermined time period”]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Kim’s teachings of memory training techniques with the teachings of Hiraishi and Mizumoto, for the purpose of eliminating the skew between the strobe signal and the data signal, thereby having more accurate sampling of the data.
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hiraishi and Mizumoto as applied to claim 15 above, and further in view of Kim.
Regarding Claim 19, Hiraishi discloses wherein the semiconductor memory apparatus comprises a data receiving circuit (Figure 1, item 19) configured to receive the data input (Figure 1, item DQ[7:0]) according to a plurality of multi-phase clock signals (Figure 1, items DQS1-DQS4) to generate received data (Figure 2, paragraph 0018; i.e., the receiver replica circuit 44 is a replica of the data DQ receiver 19; both of these circuits latch the incoming data at the designated strobe timing points, which are based on the multi-phase DQS signals);
a strobe signal processing circuit (Figure 1, item 21) configured to generate the plurality of multi-phase clock signals by dividing the data strobe signal (Figure 1, item DQS_t and DQS_c) into divided signals (Figure 1, item 22) and delaying (Figure 1, item 23) the divided signals by a predetermined time period (paragraphs 0017 and 0019; i.e., the incoming data strobe signal is divided into four-phase strobe signals DQS1-DQS4, which can further be delayed by a predetermined time period determined by delay circuit 23).
Hiraishi and Mizumoto do not expressly disclose a skew detection circuit configured to generate a replication clock signal corresponding to one of the plurality of multi-phase clock signals according to the write training internal processing enable command and configured to generate skew information according to the replication clock signal.
In the same field of endeavor (e.g., memory training techniques), Kim teaches a skew detection circuit (Figure 3, item 400, paragraph 0053) configured to generate (Figure 3, item 410, paragraph 0054) a replication clock signal (Figure 3, item DQS_re, paragraph 0053) corresponding to a clock signal (paragraph 0053; i.e., a replica of a data strobe clock signal [see Figure 4, item DQS_CLK]) according to the write training internal processing enable command (Figure 3, item RESET, paragraph 0055) and configured to generate skew information according to the replication clock signal (paragraph 0053; i.e., the skew information D_CODE is generated based on the generated replication clock signal DQS_re).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Kim’s teachings of memory training techniques with the teachings of Hiraishi and Mizumoto, for the purpose of eliminating the skew between the strobe signal and the data signal, thereby having more accurate sampling of the data.
Regarding Claim 20, Kim teaches wherein the skew detection circuit comprises a strobe signal replication circuit configured to generate the replication clock signal during a time period during which an oscillation enable signal is active (Figure 4, item ST_S, paragraph 0055);
a counter configured to generate the skew information by counting edges of the replication clock signal during the time period during which the oscillation enable signal is active (paragraph 0088); and
a timing control circuit (Figure 3, item 420) configured to generate the oscillation enable signal in response to a plurality of timing control signals (Figure 3, items PDLPF, VAL, and AMB, paragraph 0055).
Response to Arguments
Applicant's arguments filed 6/2/26 have been fully considered but they are not persuasive.
Regarding Claim 1, Applicant argues "Kim, however, teaches that the DCDL 320 may receive the buffered data DQB from the DQ buffer group 310 and correct skew of the data DQB by controlling a delay time of the data according to a delay code D_CODE. The delay code D_CODE is generated according to the rising data and falling data output from the sampler 300 regardless of the replica clock signal DQS_re." Response, page 10. The examiner disagrees. Contrary to Applicant's argument, Kim does in fact teach the argued feature. Kim states "[t]he de-skew circuit 400 may generate a data replica clock DQ_re and a data strobe replica clock DQS_re, and may output a delay code D_CODE for skew correction according to the rising data R_DATA and the falling data F_DATA which are fed back from the sampler 330." Kim, paragraph 0053. Kim further states "[t]he sampler 330 may sample the delay data D_DQB in response to a delay data strobe clock D_DQSB. For example, the sampler 330 may sample the delay data D_DQB to output rising data R_DATA and falling data F_DATA." Id. at paragraph 0052. "The data strobe replica clock DQS_re may be used by the DQS CLK output circuit 350." Id. at paragraph 0053. "The DQS CLK output circuit 350 may output the delay data strobe clock D_DQSB to the sampler 330 in response to the data strobe replica clock DQS_re and the buffered data strobe signal DQSB." Id. at paragraph 0058. As can be seen, the sampler 330 will only output the rising and falling data R_DATA and F_DATA (which are used by the skew controller 420 to generate the skew information D_CODE) when it receives the delay data strobe clock D_DQSB. The DQS CLK Output Circuit 350 will only output the delay data strobe clock D_DQSB when it receives the replica clock signal DQS_re from CLK generator 410. Accordingly, the skew information D_CODE is generated "according to the replication clock signal" DQS_re, as required by the claim.
Regarding Claim 2, Applicant argues “[t]he Office Action relies on paragraph [0020] of Choe as teaching ‘the skew detection circuit is configured to output the skew information to an external device in response to external control’ as set forth in dependent claim 2. This paragraph, however, does not support output of skew information to an external device in response to external control.” Response, page 11. The examiner disagrees. Contrary to Applicant’s argument, Choe does in fact teach the argued limitation. Choe teaches that skew information is provided to the memory (which is “external” to the memory controller) that adjusts the phase (to correct for skew) by training the memory, which occurs based on external training instructions from the memory controller. See Choe, paragraph 0020. Accordingly, Applicant’s argument is not persuasive.
Regarding Claim 3, Applicant argues “Kim, however, does not teach or suggest counting edges of the replication clock signal to generate skew information, but rather generates the D_CODE according to the rising data and the falling data, as described above. Further, as shown in FIG. 4 to FIG. 7 of Kim, the replica clock signal DQS_re is not input to the skew controller 420. Thus, the skew controller 420 cannot generate the D-CODE by counting edges of the replica clock signal DQS_re.” Response, page 11. The examiner disagrees. Kim teaches that the timer TM (equivalent to the claimed “counter”), which is a part of the skew controller 420 that generates the skew information D_CODE, counts the rising and falling edges R_DATA and F_DATA and the number of edges of the common clock CLKcom. See Kim, paragraph 0088. Kim further teaches that the common clock CLKcom and the replication clock DQS_re are the same. See id. at paragraph 0094. Accordingly, Kim teaches a counter that counts edges of the replication clock in order to output the skew information D_CODE.
Regarding Claims 6 and 15, Applicant argues "Mizumoto, however, teaches that during the period of write training, writing and reading data in the memory 90 is prevented from the memory controller 70. The write request corresponding to the "NORMAL CONTROL" period in FIG. 5 is not the program operation of the claims, but test data writing only for the write training. Therefore, Hiraishi and Mizumoto cannot perform the write training operation during the program operation period." The examiner disagrees. The argued claims do not require that writing and reading need to occur during time period in which normal operation is performed. Mizumoto states "[i]n the period of the write training, the central bus-control system 50 grants the access right only in response to the write request issued by the master A 20, in which the real-time property needs to be ensured". Mizumoto, paragraph 0071. This "real-time property" corresponds to "normal" processing such as image display and video input. See id. at paragraph 0020. During write training, "when viewed from the master A 20 having issued the write request, the write data is written in the memory 90 at the time of the storage of the write request in the buffer 71, allowing write access during the write training as in a normal operation." Id. at paragraph 0076. Therefore, the master A 20 is executing normal program operations (e.g., transmitting write data to the memory controller 70 for image and video processing) even though that write data is not immediately transmitted to the memory 90. Accordingly, it can be seen that Mizumoto does in fact teach "performing the write training operation during a time period during which the normal operation is performed" and further "wherein the normal operation includes a program operation", as required by the claims.
Regarding Claim 7, Applicant argues “Hiraishi and Mizumoto fail to teach or suggest ‘the normal operation further includes a normal data output operation and an erase operation’ as set forth in dependent claims 7 and 16 because Hiraishi and Mizumoto cannot perform the write training operation during the data output operation period and the erase operation period.” Response, page 12. The examiner disagrees. Contrary to Applicant’s argument Mizumoto does in fact teach the argued features. Mizumoto teaches that the master A 20 is allowed to perform a normal data output operation such as a write while the write training is occurring. See Mizumoto, paragraphs 0071 and 0076. Further, Mizumoto teaches a write request can be deleted/erased, which is equivalent to the claimed “erase operation”. See id. at paragraph 0103. Accordingly, Applicant’s argument is not persuasive.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN whose telephone number is (571)272-6495. The examiner can normally be reached Monday - Friday, 8 am - 5 pm, alternate Fridays.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached at 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175
Prosecution Insights