DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/4/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-16 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US Publication No. 2023/0299085) in view of Yang (US Publication No. 2022/0223706).
Regarding claim 1, Xie discloses a semiconductor device, comprising (Figure 21):
a substrate (102)
a source electrode (126) and a drain electrode (126) spaced apart from each other on the substrate (102)
a channel (114/116/118) between the source electrode (126) and the drain electrode (126), the channel including a two-dimensional material
a gate electrode (164) between the source electrode (126) and the drain electrode (126), wherein the channel includes a plurality of first channel layers (114) and a plurality of second channel layers (138)
the plurality of the first channel layers (114/116/118) are parallel to each other and spaced apart from each other
the plurality of the second channel layers (138) are perpendicular to the plurality of the first channel layers and between the plurality of the first channel layers (114)
the gate electrode (164) is on a first surface of each of the plurality of first channel layers (114/116/118) and a second surface of each of the plurality of first channel layers
the gate electrode (164) is on a first surface of each of the plurality of second channel layers (138) and a second surface of each of the plurality of second channel layers
Xie does not clearly disclose second channel layers alternately provided at a first end of each of the plurality of first channel layers and second end of each of the plurality of first channel layers. However, Yang discloses channel layers (P11 middle) alternatively provided at a first end of each of the first channel layers so they are perpendicular to each other (Figure 18). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the channels of Xie to include the perpendicular channel configuration of Yang, since it enhances the driving current of the transistor and improves electrical performance related to carrier mobility (paragraph 26).
Regarding claim 2, Xie discloses gate insulation material (154) is between the channel (114) and the gate electrode (164).
Regarding claim 3, Xie discloses a spacer (124) between the channel (114) and the gate insulation material (154).
Regarding claim 4, Yang discloses the plurality of the first channel layers (P11) are parallel to a top surface of the substrate (10) (Figure 10). As discussed above, it would have been obvious to combine Xie in view of Yang.
Regarding claim 5, Xie discloses the channel further includes a plurality of third channel layers (P11 second layer) spaced apart from the plurality of the first channel layers (P11 first layer), a plurality of fourth channel layers (P12 second layer) between the plurality of the third channel layers (P11 second layer) in a direction perpendicular to the plurality of the third channel layers, and a central channel layer (P12 second layer) above the plurality of the first channel layers and the plurality of the third channel layers, the plurality of fourth channel layers (P12 second layer)) , respectively, are alternately provided at a first end of each of the plurality of third channel layers and a second end of each of the plurality of third channel layers (P11 second layer), and the plurality of second channel layers and the plurality of fourth channel layers are provided symmetrically with respect to a center of the central channel layer (Figure 20).
Regarding claim 6, Xie discloses the plurality of the first channel layers (114/116/118) are perpendicular to a top surface of the substrate (Figure 21).
Regarding claim 7, Xie/Yang discloses the limitations as discussed in the rejection of claim 1 above. Xie/Yang does not disclose the two-dimensional material has a bandgap of 0.1 eV or more. However, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the bandgap of the two-dimensional material to have a bandgap in this range to control how electrons move and absorb light in ultrathin applications for turning nanoscale transistors on and off efficiently, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 8, Xie/Yang discloses the limitations as discussed in the rejection of claim 1 above. Xie/Yang is silent regarding the two-dimensional material comprises MoS2, MoSe2, MoTe2, WS2, or black phosphorus, or a combination thereof. However, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the two-dimensional material to comprise on of these materials to control how electrons move and absorb light in ultrathin applications for turning nanoscale transistors on and off efficiently, since it has been held that the provision of adjustability, where needed, involves routine skill in the art . In re Stevens, 101 USPQ 284 (CCPA 1954).
Regarding claim 9, Xie/Yang discloses the limitations as discussed in the rejection of claim 1 above. Xie/Yang does not disclose in a cross-sectional cut across between the source electrode and the drain electrode, a length of one of the plurality of first channel layers is between 10 nm and 500 nm. However, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the length of one of the channel layers to be within this range to control how electrons move and absorb light in ultrathin applications for turning nanoscale transistors on and off efficiently, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 10, Xie/Yang discloses the limitations as discussed in the rejection of claim 1 above. Xie/Yang does not disclose a cross-section cut across between the source electrode and the drain electrode, a length of one of the plurality of second channel layers is between 5 nm or more and 50 nm or less. However, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the length of one of the channel layers to be within this range to control how electrons move and absorb light in ultrathin applications for turning nanoscale transistors on and off efficiently, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 11, Xie discloses a method of manufacturing a semiconductor device, the method comprising:
stacking a first sacrificial layer (108) and a second sacrificial layer (140) on a substrate (102)
removing the second sacrificial layer (Figure 10)
forming a channel (138) including a two-dimensional material on the first sacrificial layer (108)
removing the first sacrificial layer (Figures 9-10)
forming a gate electrode (164) between a source electrode (126) and a drain electrode (126) on the substrate (102)
wherein the forming the channel includes forming a plurality of first channel layers and a plurality of second channel layers
the plurality of the first channel layers (114/116/118) are parallel to each other and spaced apart from each other
the plurality of the second channel layers (138) are perpendicular to the plurality of the first channel layers and between the plurality of the first channel layers (114)
the forming the gate electrode (164) includes forming the gate electrode on a first surface of each of the plurality of the first channel layers (114/116/118), a second surface of each of the plurality of the first channel layers, a first surface of each of the plurality of the second channel layers (138), and a second surface of each of the plurality of the second channel layers (138)
Xie does not clearly disclose second channel layers alternately provided at a first end of each of the plurality of first channel layers and second end of each of the plurality of first channel layers. However, Yang discloses channel layers (P11 middle) alternatively provided at a first end of each of the first channel layers so they are perpendicular to each other (Figure 18). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the channels of Xie to include the perpendicular channel configuration of Yang, since it enhances the driving current of the transistor and improves electrical performance related to carrier mobility (paragraph 26).
Regarding claim 12, Xie discloses forming a gate insulation material (154) on the channel before the forming the gate electrode (164) (Figures 19-21), wherein the forming the gate electrode (164) includes forming the gate electrode on the gate insulation material (154) so the gate insulation material (154) is between the channel (114) and the gate electrode (164).
Regarding claim 13, Yang discloses the plurality of the first channel layers (P11) are parallel to a top surface of the substrate (10) (Figure 10). As discussed above, it would have been obvious to combine Xie in view of Yang.
Regarding claim 14, Xie discloses the plurality of the first channel layers (114/116/118) are perpendicular to a top surface of the substrate (Figure 21).
Regarding claim 15, Xie/Yang discloses the limitations as discussed in the rejection of claim 11 above. Xie/Yang does not disclose the two-dimensional material has a bandgap of 0.1 eV or more. However, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the bandgap of the two-dimensional material to have a bandgap in this range to control how electrons move and absorb light in ultrathin applications for turning nanoscale transistors on and off efficiently, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 16, Xie/Yang discloses the limitations as discussed in the rejection of claim 11 above. Xie/Yang is silent regarding the two-dimensional material comprises MoS2, MoSe2, MoTe2, WS2, or black phosphorus, or a combination thereof. However, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the two-dimensional material to comprise on of these materials to control how electrons move and absorb light in ultrathin applications for turning nanoscale transistors on and off efficiently, since it has been held that the provision of adjustability, where needed, involves routine skill in the art . In re Stevens, 101 USPQ 284 (CCPA 1954).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Jain et al. (US Publication No. 2025/0040167) discloses horizontal nanosheets in a serpentine pattern (Figure 2). Liaw (US Publication No. 2021/0313333) discloses nanosheets with parallel and perpendicular portions (Figure 4E).
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/N.R.P/ 8/23/2026Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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