DETAILED ACTION
Claims 21-40 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application (16/537,481) under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Information Disclosure Statement
Per MPEP 609.02(I) and (II)(A)(2), the examiner of a continuing application will consider information which has been considered by the Office in the parent application. Therefore, information considered in parent application 16/537,481 has been considered during examination of the instant application. However, if applicant wants said considered information to be printed on any patent resulting from the instant application, applicant must ensure that said information appears on either an IDS or an 892 in the instant application.
Specification
The title of the invention is not sufficiently descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure is objected to because of the following informalities:
In paragraph 1, insert patent numbers for any applications that have issued.
In paragraph 231, please correct “the there”.
Appropriate correction is required.
Drawings
The drawings are objected to because of the following minor informalities:
In FIG.6, please fit the text “Core 14 Cntrlr” into its respective box (37 CFR 1.84(p)(3)).
In FIG.10, box 1040, insert the missing closed parenthesis.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Please ensure any replacement is in only black and white to avoid pixelation and further objection. The figure or figure number of an amended drawing should not be labeled as “amended.” Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 22 is objected to because of the following informalities:
In lines 5-6, “and the global channel further comprising” should be replaced with
--wherein the global channel further comprises--.
In lines 8-9, “each respective partial dot product value” incorrectly includes respective dot product values from claim 21. In other words, claim 22 states that each partial value, including each generated by the first plurality of dot product cores (from claim 21), is generated by the second plurality of dot product cores. Thus, in claim 22, the examiner recommends claiming the partial values as second partial values (or the like) so as to distinguish them from those in claim 21.
Claim 32 is objected to because of the following informalities:
In line 1, insert a comma after “comprising” for consistency with other claims.
The 2nd to last paragraph should be reworded to improve grammar and flow/readability. The examiner recommends --receiving by the second dot product bus, from the first dot product bus, the first aggregated dot product output; and--, OR --sending, by the first dot product bus to the second dot product bus, the first aggregated dot product output; and--.
Claim 34 is objected to because of the following informalities:
In line 4, insert --to-- after “which”.
Claim 39 is objected to because of the following informalities:
In line 1, replace “31:” with --31, comprising:--.
Claim 40 is objected to because of the following informalities:
At the end of line 8, replace the colon with a semicolon.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Such claim limitation(s) is/are:
In claim 23 (and similarly claim 33), “the fabric controller receives neural network program instructions…”. The examiner has been unable to find any particular structure disclosed in the specification that performs this function. For instance, paragraph 98 simply says the controller receives the instructions, but gives no details on what the controller actually comprises to perform the receiving. FIGs.4 and 6 shows the fabric controller as a black box. As such, due to lack of adequate disclosure for purposes of 112(f) interpretation, broadest reasonable interpretation (BRI) of this limitation is taken and 112(a)/(b) rejections appear below. The examiner recommends inserting --circuit-- after “controller” to avoid 112(f) interpretation.
In claim 24 (and similarly claim 34), “the first cluster controller generates configuration data…”. The examiner has been unable to find any particular structure disclosed in the specification that performs this function. For instance, paragraph 104 simply says the cluster controller decomposes instructions to determine the configuration data, but gives no details on what the controller actually comprises to perform the generating. FIGs.6-7 and 9 shows the cluster controller as a black box. As such, due to lack of adequate disclosure for purposes of 112(f) interpretation, BRI of this limitation is taken and 112(a)/(b) rejections appear below. The examiner recommends inserting --circuit-- after “controller” to avoid 112(f) interpretation.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 23-30 and 33-38 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 23-24 and 33-34, as described above in the “Claim Interpretation” section, the disclosure does not provide adequate structure for the fabric/cluster controller to perform the claimed function(s). The specification does not demonstrate that applicant has made an invention that achieves the claimed function(s) because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention.
Claims 25-30 and 35-38 are rejected due to their dependence on a claim lacking adequate written description.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 23-30 and 33-39 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 23-24 and 33-34, the controller + function limitations invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure(s), material(s), or act(s) for performing the entire claimed function(s) and to clearly link the structure(s), material(s), or act(s) to the function(s). Therefore, the claim(s) are indefinite and are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim(s) so that the claim limitation(s) will no longer be interpreted as a limitation(s) under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g. claim the controllers as circuits);
(b) Amend the written description of the specification such that it expressly recites what structure(s), material(s), or act(s) perform the entire claimed function(s), without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure(s), material(s), or act(s) disclosed therein to the function(s) recited in the claim(s), without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure(s), material(s), or act(s) and clearly links them to the function(s) so that one of ordinary skill in the art would recognize what structure(s), material(s), or act(s) perform the claimed function(s), applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure(s), material(s), or act(s) for performing the claimed function(s) and clearly links or associates the structure(s), material(s), or act(s) to the claimed function(s), without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure(s), material(s), or act(s), which are implicitly or inherently set forth in the written description of the specification, perform the claimed function(s). For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 39, “the second partial dot product value”. The examiner believes applicant may have meant to claim --the third partial dot product value-- based on line 5 and the last line. The examiner will interpret the claim as if “third” was used.
Claims 25-30 and 35-38 are rejected due to their dependence on an indefinite claim.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 21, 23, 31, 33, and 40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 4 of U.S. Patent No. 12,093,696 in view of the examiner’s taking of Official Notice.
Claim 21 is mostly anticipated by claim 4 of ‘696. The only substantial difference between the two is that claim 4’s post-processor (from claim 1) does not necessarily compute output values based on the first aggregate dot product output. However, Official Notice is taken that such post-processing was well known in the art of neural networks before applicant’s invention. Such could include performing an activation function on the dot product so as to properly implement a neural network. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify claim 4 of ‘696 such that the post-processor computes output values based on the first aggregates dot product output. While claim 4 of ‘696 does not include all terminology found in claim 21, such as “global channel”, this is merely a name for the circuitry that does exist in ‘696, and, thus, it is not a patentable distinction.
Claim 23 is anticipated by claim 4 of ‘696, which includes cores that would execute software based on the neural network to be implemented. Thus, there must exist some controller that receives the software and assigns work to the cores.
Claims 31 and 33 are methods performed by claims 21 and 23, respectively. Thus, they are not patentable over claim 4 of ‘696 for similar reasoning given above.
Claim 40 is a medium corresponding to control the circuit of claims 21 and 23, respectively. Thus, claim 40 is mostly not patentable over claim 4 of ‘696, for similar reasoning given above. Further, the software used to control the circuit is necessarily stored on a medium.
Claims 21, 23, 31, 33, and 40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 11 of U.S. Patent No. 11,205,115 in view of the examiner’s taking of Official Notice.
Claim 21 is mostly anticipated by claim 11 of ‘115. The only substantial difference between the two is that claim 21 requires writing output values to a first core circuit memory. In claim 11 of ‘115, the outputting is disclosed, but not to memory. However, Official Notice is taken that storing output data to memory so that it can be accessed at the convenience of subsequent logic for processing was well known in the art of neural networks before applicant’s invention. This decouples the operations of the cores, thereby allowing the data to wait in a stored state until a core is ready to operate on it. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify claim 11 of ‘115 such that the output values are written to a first core circuit memory. While claim 11 of ‘115 does not include all terminology found in claim 21, such as “global channel”, this is merely a name for the circuitry that does exist in ‘115, and, thus, it is not a patentable distinction.
Claim 23 is anticipated by claim 11 of ‘115, which includes cores that would execute software based on the neural network to be implemented. Thus, there must exist some controller that receives the software and assigns work to the cores.
Claims 31 and 33 are methods performed by claims 21 and 23, respectively. Thus, they are not patentable over claim 11 of ‘115 for similar reasoning given above.
Claim 40 is a medium corresponding to control the circuit of claims 21 and 23, respectively. Thus, claim 40 is mostly not patentable over claim 11 of ‘115, for similar reasoning given above. The software used to control the circuit is necessarily stored on a medium.
Claims 21, 23, 31, 33, and 40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 11 of U.S. Patent No. 11,501,138. Though not exact claims, claim 11 of ‘138 anticipates the aforementioned of the instant application. Any differences in wording, such as “global channel”, relate to non-distinctive naming conventions.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 21-23, 31-33, and 39-40 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception without significantly more.
Regarding step 1 of the subject matter eligibility test in MPEP 2106, all claims are directed to a statutory category of invention.
Regarding claim 21:
With respect to step 2A (prong 1) of the test, the claim recites “computes a first partial dot product value for a first computational node of a first layer of a neural network”, “aggregates respective partial dot product values for the first computational node, each respective partial dot product value generated to generate a first aggregated dot product output”, and “computes output values for the first computational node of the neural network based on the first aggregated dot product output”. Dot product calculations comprise multiplication and accumulation, and computing the output values comprises at least biasing, scaling, pooling, or applying non-linear activation functions (paragraphs 9 and 108 of the specification). Thus, each of these constitutes an abstract idea that can be grouped into at least one of the grouping of mathematical concepts or mental processes (MPEP 2106.04(a) and (a)(2)).
With respect to step 2A (prong 2) of the test, the additional elements claimed include “a neural network integrated circuit comprising: a first core circuit cluster of a set of core circuit clusters, the first core circuit cluster comprising a first plurality of dot product cores, a global channel comprising at least a first channel segment for the first core circuit cluster, wherein the first channel segment comprises (i) a first dot product bus, (ii) a first post-processor, and (iii) a first activation write bus that writes the output values to a first core circuit memory”. All elements are claimed in some fashion to perform the identified abstract idea(s). However, these elements constitute generic computing components that are used to implement the abstract idea(s). Per the courts, such does not integrate the judicial exception into a practical application (MPEP 2106.04(d)(I), 6th bullet). Furthermore, writing the output values to a first core circuit memory amounts to insignificant post-solution activity that is a mere nominal or tangential addition to the claim. Per the courts, such activity does not integrate the judicial exception into a practical application (MPEP 2106.04(d)(I), 7th bullet).
With respect to step 2B of the test, the courts have determined that generic computing components to implement the exception and well-understood, routine, conventional activity do not amount to significantly more (MPEP 2106.05(I)(A), elements (i) and (ii) in the 2nd enumerated list). Further, storing information in memory has been deemed by the courts to be well-understood, routine, and conventional (MPEP 2106.05(d)(II), element (iv) in the 1st enumerated list). As such, these additional limitations, considered alone or in combination, do not amount to significantly more than the judicial exception itself. Thus, claim 21 is not patent-eligible under 35 U.S.C. 101.
Regarding claim 22, the claim recites math (partial product generation, various aggregation operations) and generic hardware to do the math. For reasoning set forth above, such, alone or in combination with other limitations, does not integrate into a practical application or amount to significantly more than the abstract idea.
Regarding claim 23, applicant claims a fabric controller that receives instructions that assign a set of computation nodes to the set of core circuit clusters. Instructions that assign work amounts to mere instructions to implement the abstract idea on a computer (e.g. instructions for dot products, for instance, assign dot product computation nodes to cores). Such an instruction has been held by the courts to not integrate into a practical application or amount to significantly more (similar to generic computing components). A generic fabric controller is also generic and thus does not integrate or amount to significantly more. Finally, receiving instructions would amount to insignificant extra-solution activity that does not integrate or amount to significantly more (MPEP 2106(d)(II), elements (i) and (iv) in the 1st enumerated list).
Claim 31 is not patentable for similar reasoning as claim 21.
Claims 32-33 and 39 are not patentable for similar reasoning given above (abstract ideas, generic computing components, and extra-solution activities, are being claimed). With respect to claim 39, claiming that multiple operations occur serially during different clock cycles comprises more generic computing that does not integrate or amount to significantly more.
Claim 40 is not patentable for similar reasoning as claim 21. The medium for storing instructions that cause activities to occur is a generic computing component.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21, 23, 31, 33, and 40 are rejected under 35 U.S.C. 103 as being unpatentable over Nomura et al. (US 2019/0156180) in view of Appuswamy et al. (US 2019/0303741).
Referring to claim 21, Nomura has taught a neural network integrated circuit comprising:
a plurality or dot product cores to compute dot product values for a first computational node of a first layer of a neural network (see FIGs.4-5 and paragraph 51. The computational nodes (operations) of neural network layers (FIG.5) are assigned to cores. The cores will then perform dot products (multiply followed by accumulation/addition), which are foundational operations of neural network processing).
Nomura has not taught a first core circuit cluster of a set of core circuit clusters, the first core circuit cluster comprising a first plurality of dot product cores, wherein a first dot product core of the first plurality of dot product cores computes a first partial dot product value for a first computational node of a first layer of a neural network. However, Appuswamy has taught using a core circuit cluster including cores that each calculate a partial dot product. The partial dot products are then sent to a final core to accumulate/aggregate the partial dot products (see FIG.2 and paragraphs [0032]-[0043]). This would provide the benefit of determining many partial dot products at the same time so as to speed up the overall calculation. One would find motivation to implement this type of multi-core parallel processing where many inputs are provided to a given node, e.g. in a fully connected layer with many nodes/neurons, where a node may not have the resources necessary to perform all partial dot products at the same time. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nomura to include a first core circuit cluster of a set of core circuit clusters, the first core circuit cluster comprising a first plurality of dot product cores, wherein a first dot product core of the first plurality of dot product cores computes a first partial dot product value for a first computational node of a first layer of a neural network. That is, there may be many cores in Nomura (FIG.4 shows a network of cores that can continue in each direction (the more cores, the more computations that can be performed in parallel so as to accommodate larger neural networks). Where a node of the network in FIG.5 is shown to be assigned to a core, the examiner asserts that it is obvious for this core to actually be a cluster of cores that calculate the dot product in parallel as described in Appuswamy.
Nomura, as modified, has further taught a global channel comprising at least a first channel segment for the first core circuit cluster, wherein the first channel segment comprises (i) a first dot product bus that aggregates respective partial dot product values for the first computational node, each respective partial dot product value generated by a respective dot product core of the first plurality of dot product cores to generate a first aggregated dot product output (again see the combination above. One of the cores receives all of the partial dot products to aggregate them. The circuitry that aggregates is considered part of a first dot product bus), (ii) a first post-processor that computes output values for the first computational node of the neural network based on the first aggregated dot product output (see paragraphs 51-53, for instance. A first “post-processor” will perform an activation function on the dot products, as is known in the art of neural network processing (the post-processor may be at least part of the core that aggregates the partial dot products, or another core)), and (iii) a first activation write bus that writes the output values to a first core circuit memory (output data is routed between cores to process multiple layers. To route between cores, routers are used (e.g. FIGs.6, 8 and 9), and FIG.9 shows memory to which output data is stored (e.g. 54, 72, 74)). Any of these may be called a first core circuit memory).
Referring to claim 23, Nomura, as modified, has taught the neural network integrated circuit of claim 21, comprising a fabric controller, wherein the fabric controller receives neural network program instructions for the first layer of the neural network, wherein the neural network program instructions assign a set of computational nodes for the first layer to the set of core circuit clusters (FIG.5 is a core array that executes instruction operations. Thus, instructions implementing a neural network model correspond to operations to be assigned to the clusters).
Claims 31 and 33 are rejected for similar reasoning as claims 21 and 23, respectively.
Claim 40 is mostly rejected for similar reasoning as claim 21. Nomura has further taught a computer program product comprising at least one non-transitory computer-readable storage medium storing software instructions that, when executed, cause a neural network integrated circuit to perform the claimed operations (all operations of the neural network device will be triggered by software code stored on a medium)).
Allowable Subject Matter
Claims 22, 24-30, 32, and 34-39 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Cassidy (US 2019/0385046) has taught reconfigurable core-level and vector-level parallelism, including core islands for performing dot products.
Lie (US 2018/0314941) has taught accelerated deep-learning using PEs and routers for determining and propagating partial sums (e.g. FIG.11).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
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