DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-11, and 15-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by BANG (U.S 2023/0200182 A1).
As to claim 1, BANG discloses in Figs. 4-5 and 7 a display device comprising: a substrate (101) including a display area (AA) (Fig. 4, para. [0078]), an optical area (“area B”, para. [0005], [0010], [0087]) in the display area (AA) and including a through-hole (“hole”/“camera hole” CH, Figs. 4-5), and a non-display area (NA, Fig. 4) that surrounds the display area (AA) (Fig. 4-5, para. [0083], [0086]-[0087]); a plurality of insulation layers (comprising layers 101-107) on the substrate (101) (Fig. 7, para. [0062]-[0063]); at least one dam (301/302) on the plurality of insulation layers (comprising layers 101-107) (Fig. 7, para. [0088]); and at least one anti-connection part (“first cut-out part” 201, Figs. 5, 7) on the plurality of insulation layers (comprising layers 101-107), the at least one anti-connection part (“first cut-out part” 201) closer to the through-hole (“hole”/“camera hole” CH) than the at least one dam (301/302) (see Figs. 5, 7, para. [0088]-[0094]), wherein first trenches (see “first trenches” as annotated in Fig. 7 below) are in some (layers 106 & 107) of the plurality of insulation layers (comprising layers 101-107) that overlap the at least one anti-connection part (“first cut-out part” 201) in the optical area (“area B”, Figs. 5, 7) (see Fig. 5 and annotated Fig. 7 below).
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As to claim 2, as applied to claim 1 above, BANG discloses in Figs. 5 and 7 all claimed limitations including the limitation: wherein the plurality of insulation layers (comprising layers 101-107) comprise at least one of a first buffer layer (“lower buffer layer” 103) (Fig. 7, para. [0106]), a first gate insulation layer (“lower gate insulating film” 104) (Fig. 7, para. [0066][, 0106]), a first interlayer insulation layer (“first lower interlayer insulating film” 105) (Fig. 7, para. [0106]), a second buffer layer (“upper buffer layer” 107) (Fig. 7, para. [0106]), a second gate insulation layer (“upper gate insulating film” 137) (Fig. 3, para. [0066]), and a second interlayer insulation layer (“ second lower interlayer insulating film” 106) on the substrate (101) (Fig. 7, para. [0106]), and wherein the first trenches (see “first trenches” as annotated in Fig. 7 above) are in some insulation layers (comprising layers 106 & 107) from the plurality of insulation layers (comprising layers 101-107) that are at an upper side (top side) among the plurality of insulation layers (comprising layers 101-107) (see annotated Fig. 7 above).
As to claim 3, as applied to claim 1 above, BANG discloses in Figs. 7, 8 all claimed limitations including the display device comprising: second trenches (see “second trenches” as annotated in Fig. 8 below) in some of the plurality of insulation layers (comprising layers 106 & 107) from the plurality of insulation layers (comprising layers 101-107) that overlap the at least one dam (see “at least one dam” as annotated in Fig. 8 below) in the optical area (“area B”) (see annotated Fig. 8 below).
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As to claim 4, as applied to claims 1 and 2 above, BANG discloses in Figs. 5, 7 and 8 all claimed limitations including the display device further comprising: a first thin-film transistor (comprising 121, 122, 123 & 124, Fig. 3) on the substrate (101) in the display area (AA), the first thin-film transistor (comprising 121, 122, 123 & 124, Fig. 3) comprising a first active layer (“first semiconductor layer “ 123) (Fig. 3, para. [0059]), a first gate electrode (122), a first source electrode (121), and a first drain electrode (124) (Fig. 3, para. [0079]); at least one insulation layer (105) on the first gate electrode (122) (Fig. 3, para. [0056], [0067]-[0068]); and a second thin-film transistor (130) on the at least one insulation layer (105) (Fig. 3, para. [062]), the second thin-film transistor (130) comprising a second active layer (“second semiconductor layer” 133) (Fig. 3, para. [0062]), a second gate electrode (132) (Fig. 3, para. [0062]), a second source electrode (131), and a second drain electrode (134) (Fig. 3, para. [0063]-[0064]); a first planarization layer (110) above the first source electrode (121) and the first drain electrode (124) of the first thin-film transistor (comprising 121, 122, 123 & 124, Fig. 3) and the second source electrode (131) and the second drain electrode (134) of the second thin-film transistor (130), (Fig. 3, para. [0107]) and a second planarization layer (171) above the first planarization layer (110) (Figs. 3 and 7-8, para. [0076]), wherein at least any one of the first planarization layer (110) and the second planarization layer (171) is in a first trench from the first trenches (see “first trenches” as annotated in Fig. 7 above) and fills the first trench (see Figs. 3 & 8, and annotated Fig. 7 above).
As to claim 5, as applied to claims 1 and 3 above, BANG discloses in Figs. 5, 7 and 8 all claimed limitations including the display device further comprising: first metal layers (“anodes” 151 may be formed in a multi-layered structure, para. [0054], [0072]) in each of the first trenches (see “first trenches” as annotated in Fig. 7 above) and the second trenches (see “second trenches” as annotated in Fig. 8 above), the first metal layers (“anodes” 151) along surfaces of some of the plurality of insulation layers (layers 101-107) (Figs. 3, 7-8, para. [0054], [0070], [0072]).
As to claim 6, as applied to claims 1, 3 and 5 above, BANG discloses in Figs. 5, 7, and 8 all claimed limitations including the limitation: wherein the first metal layers (“anodes” 151, para. [0054], [0072]) are in each of the first trenches (see Figs. 3 & 8; and annotated Fig. 7 above, and para. [0070]) and the second trenches (see “second trenches” as annotated in Fig. 8 above) and adjoin the surfaces of the plurality of insulation layers (layers 101-107) (see annotated Figs. 7-8 above, para. [0054], [0070], [0072]).
As to claim 7, as applied to claims 1, 3, 5 and 6 above, BANG discloses in Figs. 5 and 7 all claimed limitations including the display device further comprising: a first thin-film transistor (comprising 121, 122, 123 & 124, Fig. 3) on the substrate (101) in the display area (AA), the first thin-film transistor (comprising 121, 122, 123 & 124, Fig. 3) comprising a first active layer (“first semiconductor layer “ 123) (Fig. 3, para. [0059]), a first gate electrode (122), a first source electrode (121), and a first drain electrode (124) (Fig. 3, para. [0079]); at least one insulation layer (105) on the first gate electrode (122) (Fig. 3, para. [0056], [0067]-[0068]); and a second thin-film transistor (130) on the at least one insulation layer (105) (Fig. 3, para. [062]), the second thin-film transistor (130) comprising a second active layer (“second semiconductor layer” 133) (Fig. 3, para. [0062]), a second gate electrode (132) (Fig. 3, para. [0062]), a second source electrode (131), and a second drain electrode (134) (Fig. 3, para. [0063]-[0064]).
As to claim 8, as applied to claims 1, 3, 5, 6 and 7 above, BANG discloses in Figs. 5 and 7 all claimed limitations including the limitation: wherein a first metal layer (151) from the first metal layers (“anodes” 151, para. [0054], [0072]) is made of a same material (i.e., “Al” or “Ti”, para. [0072]) as the first source electrode (121, para. [0064]) and the first drain electrode (124, para. [0064]) (Figs. 3, 7 & 8, para. [0064], [0072]).
As to claim 9, as applied to claims 1, 3, 5, 6 and 7 above, BANG discloses in Figs. 5, 7 and 8 all claimed limitations including the display device further comprising: second metal layers (comprising “crack detection line” 410 & “connection line” 420) below each of the first trenches (see “first trenches” as annotated in Fig. 7 above) and the second trenches (see “second trenches” as annotated in Fig. 8 above) (see annotated Figs. 7 & 8 above, para. [0104]).
As to claim 10, as applied to claims 1, 3, 5, 6, 7 and 9 above, BANG discloses in Figs. 5, 7 and 8 all claimed limitations including the limitation: wherein the first metal layers (“anodes” 151, para. [0054], [0072]) are in each of the first trenches (see “first trenches” as annotated in Fig. 7 above) and the second trenches (see “second trenches” as annotated in Fig. 8 above) and adjoin side surfaces of some of the plurality of insulation layers (comprising layers 101-107) (Figs. 7-8, para. [0070]), and the first metal layers (“anodes” 151, para. [0054], [0072]) and the second metal layers (comprising “crack detection line” 410 & “connection line” 420) adjoin each other (Figs. 7 and 8, para. [0070], [0104]).
As to claim 11, as applied to claims 1, 3, 5, 6, 7, 9 and 10 above, BANG discloses in Figs. 5, 7 and 8 all claimed limitations including the limitation: wherein a first metal layer (151) from the first metal layers (“anodes” 151, para. [0054], [0072]) is on a same layer (103) and made of a same material (i.e., “Al” or “Ti”, para. [0072]) as the first source electrode (121, para. [0064]) and the first drain electrode (124, para. [0064]) {see Fig. 3, para. [0064], [0072], the first metal layer 151 may be made of the same material (i.e., “Al” or “Ti”) as the first source electrode 121}, and a second metal layer (410/420) from the second metal layers (comprising “crack detection line” 410 & “connection line” 420) is on a same layer (104) and made of a same material as the first gate electrode (122) {see Figs. 3 & 7, para. [0123], at least a second metal layer 420 may be made of the same material as the first gate electrode 122} (Figs. 3 and 7, para. [0123]-[0124]).
As to claim 15, as applied to claim 1 above, BANG discloses in Figs. 4-5 and 7 all claimed limitations including the display device further comprising: an optical electronic device (“optical sensors” , para. [0005], [0010]) that overlaps the optical area (“area B”, Figs. 4-5) (Figs. 4-5, para. [0005], [0010], [0087]).
As to claim 16, as applied to claims 1 and 15 above, BANG discloses in Figs. 4-5 and 7 all claimed limitations including the limitation: wherein, the through-hole (CH, Fig. 4) corresponds to the optical electronic device (“optical sensors” , para. [0005], [0010]) (Figs. 4-5, para. [0005]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over BANG (U.S 2023/0200182 A1) in view of JUNG et al. (U.S 2024/0121989 A1).
As to claim 12, as applied to claims 1, 3, 5, 6, 7, 9 and 10 above, BANG discloses in Figs. 5, 7 and 8 all claimed limitations including the display device further comprising: a first metal layer (151) from the first metal layers (“anodes” 151, para. [0054], [0072]) is made of a same material (i.e., “Al” or “Ti”, para. [0072]) as the first source electrode (121, para. [0064]) and the first drain electrode (124, para. [0064]) {see Fig. 3, para. [0064], [0072], the first metal layer 151 may be made of the same material (i.e., “Al” or “Ti”) as the first source electrode 121}
BANG does not disclose a light-blocking layer below the first active layer and overlaps the first gate electrode, so that a second metal layer from the second metal layers is made of a same material as the light-blocking layer.
JUNG et al. disclose in Fig. 4 a display device comprising: a light-blocking layer (BML) below the first active layer (“semiconductor regions” ACT) and overlaps the first gate electrode (GE) (Fig. 4, para. [0101], [0103], [0104]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify the reference of BANG by providing a light-blocking layer below the first active layer and overlaps the first gate electrode, as taught by JUNG et al., so that a second metal layer from the second metal layers can be made of a same material (such as “aluminum (Al)” or “titanium (Ti)” ) as the light-blocking layer. One skilled in the art would have been motivated to introduce a light blocking layer into the display device to shield the underlying active semiconductor channels from external ambient light or backlight irradiation, suppress optical interference and stabilize electrical characteristics. Furthermore, utilizing the same material (such as aluminum or titanium) for both the second metal layer from the second metal layers and the light-blocking layer is highly effective in achieving excellent thermal stability under high process temperatures.
Allowable Subject Matter
Claims 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
LEE et al. (U.S 2023/0172030 A1) disclose in Figs. 1-7 a display device comprising: a substrate (101) including a display area (AA), an optical area (B) in the display area and including a through-hole (CH), and a non-display area (NA) that surrounds the display area; a plurality of insulation layers (101-107) on the substrate (101); at least one dam (301)on the plurality of insulation layers (101-107); and at least one anti-connection part (201) on the plurality of insulation layers (101-107), the at least one anti-connection part (201) closer to the through-hole (CH) than the at least one dam (301), wherein first trenches are in some of the plurality of insulation layers (101-107) that overlap the at least one anti-connection part (201) in the optical area.
LIM et al. (U.S 2025/0185471 A1) disclose in Figs. 1-4 a display device comprising: a substrate (101) including a display area (AA), an optical area (A) in the display area and including a through-hole (CH), and a non-display area (NA) that surrounds the display area; a plurality of insulation layers (101-109) on the substrate (101); at least one dam (“DAM”, Fig. 4)on the plurality of insulation layers (101-109); and at least one anti-connection part (112/112’, Fig. 4) on the plurality of insulation layers (101-109), the at least one anti-connection part (112/112’) closer to the through-hole (CH) than the at least one dam (DAM, Fig. 4), wherein first trenches are in some of the plurality of insulation layers (101-109) that overlap the at least one anti-connection part (112/112’) in the optical area.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817 August 26, 2026
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