DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-14 are objected to because of the following informalities:
The limitations “a high logic level” in claim 1, lines 6-7 and “a low logic level” in line 7 and the same subsequent limitations should be “the high logic level” and “the low logic level” because there is only one high logic level and there is only one low logic level.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 15 is rejected under 35 U.S.C. 101 because the claim is drawn to a computer program product comprising portions of software code that are abstract instructions. Therefore, a computer program is not a physical thing (product) nor a process as they are not "acts" being performed. As such, these claims are not directed to one of the statutory categories of invention (See MPEP 2106.01), but are directed to nonstatutory functional descriptive material.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 11 and 12 recite the limitation "the write operation" in line 33, line 5 and line 1, respectively. There is insufficient antecedent basis for this limitation in the claims.
Claim 1 recites the limitation “write operations” in line 4. It is unclear whether this limitation is different from “write operations” in claim 1, line 1.
Allowable Subject Matter
Claim 1 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Regarding claim 1, the closest prior art (US 2025/0022509) made of record and considered pertinent to the applicant's disclosure teaches a method of performing write operations in a Phase Change Memory device comprising a first set of cells and a second set of cells configured to be set to a low logic level and to a high logic level, respectively, in response to write operations comprising reset write operations or set write operations (paragraph [0086]), but does not teach the claimed limitation of “considering the set write operation: i) successful, in response to the at least one set verify operation indicating that the at least one cell in the second set of cells is set to a high logic level in response to the set write operation; and ii) failed, in response to the at least one set verify operation indicating that the at least one cell in the second set of cells is set to a low logic level in response to the set write operation; verifying success or failure of the reset write operation via at least one verify operation selected out of individual and looped reset write verify operations to check if the at least one cell in the first set of cells is set to a low logic level in response to the reset write operation; considering the reset write operation: i) successful, in response to any of the individual and looped reset write verify operations indicating that the at least one cell in the first set of cells is set to a low logic level in response to the reset write operation; and ii) failed, in response to all of the individual and looped reset write verify operations indicating that the at least one cell in the first set of cells is set to a high logic level in response to the reset write operation; and considering the write operation as failed in response to the reset write operation being considered as failed and/or to the set write operation being considered as failed.” in combination with the other limitations thereof as is recited in the claim. Claims 2-14 depend on claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim (US 2024/420758) discloses a semiconductor system for inputting and outputting data.
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/HUAN HOANG/ Primary Examiner, Art Unit 2827
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